[PATCH] D144033: [AMDGPU][MC][GFX11] Add partial NSA format for image sample instructions

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

LGTM but I'd really like someone familiar with `MIMGInstructions.td` to take a look too.



================
Comment at: llvm/lib/Target/AMDGPU/GCNSubtarget.h:137
+  bool HasPartialNSAEncoding = false;
   unsigned NSAMaxSize = 0;
   bool GFX10_AEncoding = false;
----------------
Remove NSAMaxSize field?


================
Comment at: llvm/lib/Target/AMDGPU/MIMGInstructions.td:1068
+
+  // In NSA format if there is a requirement for more VGPRs then the format
+  // supports, then the rest are sequential after the last one. Generate
----------------
"... more VGPRs than ..."


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144033/new/

https://reviews.llvm.org/D144033