[PATCH] D143786: [X86] Add `TuningPreferShiftShuffle` for when Shifts are preferable to shuffles.
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 22 03:59:02 PST 2023
RKSimon added inline comments.
================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:16572
+
// Try to use bit rotation instructions.
----------------
remove newline
================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:38819
}
- }
-
- // Attempt to match against byte/bit shifts.
- if (AllowIntDomain &&
- ((MaskVT.is128BitVector() && Subtarget.hasSSE2()) ||
- (MaskVT.is256BitVector() && Subtarget.hasAVX2()) ||
- (MaskVT.is512BitVector() && Subtarget.hasAVX512()))) {
- int ShiftAmt = matchShuffleAsShift(ShuffleVT, Shuffle, MaskScalarSizeInBits,
- Mask, 0, Zeroable, Subtarget);
- if (0 < ShiftAmt && (!ShuffleVT.is512BitVector() || Subtarget.hasBWI() ||
- 32 <= ShuffleVT.getScalarSizeInBits())) {
- PermuteImm = (unsigned)ShiftAmt;
- return true;
- }
- }
-
- // Attempt to match against bit rotates.
- if (!ContainsZeros && AllowIntDomain && MaskScalarSizeInBits < 64 &&
- ((MaskVT.is128BitVector() && Subtarget.hasXOP()) ||
- Subtarget.hasAVX512())) {
- int RotateAmt = matchShuffleAsBitRotate(ShuffleVT, MaskScalarSizeInBits,
- Subtarget, Mask);
- if (0 < RotateAmt) {
- Shuffle = X86ISD::VROTLI;
- PermuteImm = (unsigned)RotateAmt;
- return true;
+ // Attempt to match against byte/bit shifts.
+ if (AllowIntDomain &&
----------------
newline
================
Comment at: llvm/lib/Target/X86/X86Subtarget.h:252
+ bool hasFasterShiftThanShuffle() const { return PreferLowerShuffleAsShift; }
// If there are no 512-bit vectors and we prefer not to use 512-bit registers,
----------------
You shouldn't need this - the GET_SUBTARGETINFO_MACRO above should have created the getter
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D143786/new/
https://reviews.llvm.org/D143786
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