[PATCH] D144550: [AArch64] Remove 64bit->128bit vector insert lowering

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, samtebbs, bipmis, david-arm, t.p.northover.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
dmgreen requested review of this revision.
Herald added a project: LLVM.

The AArch64 backend, during lowering, will convert an 64bit vector insert to a 128bit vector:

  vector_insert %dreg, %v, %idx
  =>
  %qreg = insert_subvector undef, %dreg, 0
  %ins = vector_insert %qreg, %v, %idx
  EXTRACT_SUBREG %ins, dsub

This creates a bit of mess in the DAG, and the EXTRACT_SUBREG being a machine nodes makes it difficult to simplify. This patch removes that, treating the 64bit vector insert as legal and handling them with extra tablegen patterns.

The end result is a simpler DAG that is easier to write tablegen patterns for. Unfortunately one of the tests here does get larger, because that simplification now allows it to optimize away sign_extend_inreg from a vector insert due to the bits not being demanded. In that case it now generates both SMOV and UMOV though, requiring more total instructions. This is unfortunate but seems like an unrelated issue.


https://reviews.llvm.org/D144550

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
  llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
  llvm/test/CodeGen/AArch64/srem-vector-lkk.ll

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