[PATCH] D144530: [SiFive][RISCV] Support assembler and dis-assembler for VCIX extension.

[Brandon Wu via Phabricator via llvm-commits]

4vtomat updated this revision to Diff 499404.
4vtomat added a comment.

Resolve comments by Craig.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144530/new/

https://reviews.llvm.org/D144530

Files:
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXsf.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/xsfvcp-invalid.s
  llvm/test/MC/RISCV/rvv/xsfvcp.s

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