[PATCH] D144508: [AArch64] Fix N2 SchedModel INS instruction latencies

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Sounds good to me. This LGTM but you may be able to remove the extra pattern, and it may be worth quickly adding tests for each of the 4 type sizes.



================
Comment at: llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td:1216
+// ASIMD insert, element to element
+def : InstRW<[N2Write_2cyc_1V], (instregex "^INSvi(8|16|32|64)lane$")>;
 
----------------
I don't think this line needs to be added, as it will be handled by WriteV being N2Write_2cyc_1V already. The tighter regex on `INSv..gpr` should be enough. I believe that is what it means above in:
```
// ASIMD insert, element to element
// ...
// Handled by SchedAlias<WriteV[dq], ...>
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144508/new/

https://reviews.llvm.org/D144508