[PATCH] D144092: [RISCV] Lower interleave and deinterleave intrinsics
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 21 18:05:18 PST 2023
reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.
LGTM with two test comments addressed.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll:39
+define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
+ %res = call <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
+ ret <4 x i64> %res
----------------
Missing check lines here, probably due to conflict with autogen.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll:116
+define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double> %b) {
+ %res = call <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)
+ ret <4 x double> %res
----------------
Same problem here.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144092/new/
https://reviews.llvm.org/D144092
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