[llvm] 677ea15 - [NFC][SLP]Add a test for optimistic vectorization, NFC.

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2023-02-21T11:02:32-08:00
New Revision: 677ea15e350b1014f658516604fce89a38d84afa

URL: https://github.com/llvm/llvm-project/commit/677ea15e350b1014f658516604fce89a38d84afa
DIFF: https://github.com/llvm/llvm-project/commit/677ea15e350b1014f658516604fce89a38d84afa.diff

LOG: [NFC][SLP]Add a test for optimistic vectorization, NFC.

Added: 
    llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll
new file mode 100644
index 0000000000000..db68c8aca1286
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=slp-vectorizer -S < %s -mtriple=aarch64 -aarch64-insert-extract-base-cost=3 | FileCheck %s
+
+define void @test(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[TMP1:%.*]], i64 0
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[TMP0:%.*]], i64 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[TMP2:%.*]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x i64> [[TMP2]], i64 1
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <4 x i64> [[TMP8]], i64 [[TMP5]], i32 1
+; CHECK-NEXT:    [[TMP10:%.*]] = insertelement <4 x i64> [[TMP9]], i64 [[TMP6]], i32 2
+; CHECK-NEXT:    [[TMP11:%.*]] = insertelement <4 x i64> [[TMP10]], i64 [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP12:%.*]] = insertelement <4 x i64> <i64 0, i64 0, i64 poison, i64 0>, i64 [[TMP7]], i32 2
+; CHECK-NEXT:    [[TMP13:%.*]] = or <4 x i64> [[TMP11]], [[TMP12]]
+; CHECK-NEXT:    [[TMP14:%.*]] = trunc <4 x i64> [[TMP13]] to <4 x i32>
+; CHECK-NEXT:    br label [[TMP15:%.*]]
+; CHECK:       15:
+; CHECK-NEXT:    [[TMP16:%.*]] = phi <4 x i32> [ [[TMP20:%.*]], [[TMP15]] ], [ [[TMP14]], [[TMP3:%.*]] ]
+; CHECK-NEXT:    [[TMP17:%.*]] = shufflevector <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, <4 x i32> [[TMP16]], <4 x i32> <i32 4, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP18:%.*]] = or <4 x i32> zeroinitializer, [[TMP17]]
+; CHECK-NEXT:    [[TMP19:%.*]] = add <4 x i32> zeroinitializer, [[TMP17]]
+; CHECK-NEXT:    [[TMP20]] = shufflevector <4 x i32> [[TMP18]], <4 x i32> [[TMP19]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    br label [[TMP15]]
+;
+  %4 = extractelement <2 x i64> %1, i64 0
+  %5 = or i64 %4, 0
+  %6 = trunc i64 %5 to i32
+  %7 = extractelement <2 x i64> %0, i64 0
+  %8 = or i64 %7, 0
+  %9 = trunc i64 %8 to i32
+  %10 = extractelement <2 x i64> %2, i64 0
+  %11 = extractelement <2 x i64> %2, i64 1
+  %12 = or i64 %10, %11
+  %13 = trunc i64 %12 to i32
+  %14 = extractelement <2 x i64> %0, i64 0
+  %15 = or i64 %14, 0
+  %16 = trunc i64 %15 to i32
+  br label %17
+
+17:
+  %18 = phi i32 [ %22, %17 ], [ %6, %3 ]
+  %19 = phi i32 [ %23, %17 ], [ %9, %3 ]
+  %20 = phi i32 [ %24, %17 ], [ %13, %3 ]
+  %21 = phi i32 [ %25, %17 ], [ %16, %3 ]
+  %22 = or i32 %18, 0
+  %23 = add i32 0, 0
+  %24 = add i32 0, 0
+  %25 = add i32 0, 0
+  br label %17
+}