[PATCH] D144501: [RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension

Manolis Tsamis via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Feb 21 09:06:11 PST 2023


mtsamis created this revision.
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The vendor-defined XTheadSync (no comparable standard extension exists
at the time of writing) extension adds multi-core synchronization
instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1 <https://reviews.llvm.org/D1>) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:

  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:

  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=547c18d9bb95571261dbd17f4767194037eb82bd

Depends on D144496 <https://reviews.llvm.org/D144496>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144501

Files:
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/xtheadsync-invalid.s
  llvm/test/MC/RISCV/xtheadsync-valid.s

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