[PATCH] D144033: [AMDGPU][MC][GFX11] Add partial NSA format for image sample instructions

[Jay Foad via Phabricator via llvm-commits]

foad added a reviewer: Joe_Nash.
foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:10
 #include "AMDKernelCodeT.h"
+#include "GCNSubtarget.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
----------------
I think the idea is that the assembler should not include any of the "codegen" parts of the backend. If getNSAMaxSize needs to be shared by codegen and the assembler, it should be moved into AMDGPUBaseInfo - that is why AMDGPUBaseInfo exists.


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Comment at: llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:910
       if (AddrSize > Info->VAddrDwords) {
-        // The NSA encoding does not contain enough operands for the combination
-        // of base opcode / dimension. Should this be an error?
-        return MCDisassembler::Success;
+        if (!isGFX11Plus()) {
+          // The NSA encoding does not contain enough operands for the
----------------
This should check `!hasPartialNSAEncoding`?


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Comment at: llvm/lib/Target/AMDGPU/GCNSubtarget.h:940
+      return hasGFX10_3Insts() ? 13 : 5;
+    else if (getGeneration() >= AMDGPUSubtarget::GFX11)
+      return 5;
----------------
No else after return.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144033/new/

https://reviews.llvm.org/D144033