[PATCH] D144175: [RISCV] Combine (store/load interleave, deinterleave) into vsseg2/vlseg2

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 499104.
luke added a comment.

Check if type is legal


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144175/new/

https://reviews.llvm.org/D144175

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-combine-load.ll
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed-combine-load.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-combine-store.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed-combine-store.ll

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