[PATCH] D144002: [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
Manolis Tsamis via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 20 23:35:12 PST 2023
mtsamis updated this revision to Diff 499048.
mtsamis marked 2 inline comments as done.
mtsamis added a comment.
Replace tabs with spaces and fix alignment
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144002/new/
https://reviews.llvm.org/D144002
Files:
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/xtheadmempair.ll
llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
llvm/test/MC/RISCV/rv32xtheadmempair-valid.s
llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
llvm/test/MC/RISCV/rv64xtheadmempair-valid.s
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