[PATCH] D144092: [RISCV] Lower interleave and deinterleave intrinsics

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6537
+static SDValue widenVectorOpToi8(SDValue N, SDLoc &DL, SelectionDAG &DAG,
+                                 const RISCVSubtarget &Subtarget) {
+  MVT VT = N.getSimpleValueType();
----------------
`Subtarget` is unused


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6696
+    Idx = DAG.getNode(RISCVISD::ADD_VL, DL, IdxVT, Idx,
+                      DAG.getSplatVector(IdxVT, DL, VLMAX), DAG.getUNDEF(IdxVT),
+                      OddMask, VL);
----------------
Need to pass `Idx` instead of `UNDEF` to get a mask undisturbed vadd.vv.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll:71
+; CHECK-NEXT:    vsrl.vi v12, v12, 1
+; CHECK-NEXT:    vadd.vx v16, v12, a0, v0.t
+; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
----------------
This is a mask agnostic vadd.vx. You need mask undisturbed.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D144092/new/

https://reviews.llvm.org/D144092