[llvm] fd5d92e - [X86] Precommit a test
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 20 17:00:10 PST 2023
Author: Kazu Hirata
Date: 2023-02-20T17:00:03-08:00
New Revision: fd5d92e6220905f7d942a81108266d427babe143
URL: https://github.com/llvm/llvm-project/commit/fd5d92e6220905f7d942a81108266d427babe143
DIFF: https://github.com/llvm/llvm-project/commit/fd5d92e6220905f7d942a81108266d427babe143.diff
LOG: [X86] Precommit a test
This is for:
https://github.com/llvm/llvm-project/issues/60854
Added:
Modified:
llvm/test/CodeGen/X86/select_const.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/select_const.ll b/llvm/test/CodeGen/X86/select_const.ll
index d35cd65a5db9..fbabd9b26c14 100644
--- a/llvm/test/CodeGen/X86/select_const.ll
+++ b/llvm/test/CodeGen/X86/select_const.ll
@@ -580,3 +580,18 @@ define i32 @select_ugt3_3_2(i32 %X) {
%cond = select i1 %cmp.inv, i32 3, i32 2
ret i32 %cond
}
+
+define i32 @select_eq_1_2(i32 %a, i32 %b) {
+; CHECK-LABEL: select_eq_1_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: sete %cl
+; CHECK-NEXT: movl $2, %eax
+; CHECK-NEXT: subl %ecx, %eax
+; CHECK-NEXT: retq
+
+ %cmp = icmp eq i32 %a, %b
+ %cond = select i1 %cmp, i32 1, i32 2
+ ret i32 %cond
+}
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