[llvm] c09e224 - [X86] Add test case that clobber base pointer register.

[via llvm-commits]

Author: Luo, Yuanke
Date: 2023-02-21T07:49:51+08:00
New Revision: c09e224c254c06f23a460f92abfc34e10a26192d

URL: https://github.com/llvm/llvm-project/commit/c09e224c254c06f23a460f92abfc34e10a26192d
DIFF: https://github.com/llvm/llvm-project/commit/c09e224c254c06f23a460f92abfc34e10a26192d.diff

LOG: [X86] Add test case that clobber base pointer register.

Added: 
    llvm/test/CodeGen/X86/i386-baseptr.ll

Modified: 
    llvm/test/CodeGen/X86/x86-64-baseptr.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/i386-baseptr.ll b/llvm/test/CodeGen/X86/i386-baseptr.ll
new file mode 100644
index 0000000000000..448658d93ee72
--- /dev/null
+++ b/llvm/test/CodeGen/X86/i386-baseptr.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=i386-pc-linux -stackrealign < %s | FileCheck %s
+
+declare i32 @helper() nounwind
+define void @base() #0 {
+; CHECK-LABEL: base:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %ebp
+; CHECK-NEXT:    movl %esp, %ebp
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    andl $-32, %esp
+; CHECK-NEXT:    subl $32, %esp
+; CHECK-NEXT:    movl %esp, %esi
+; CHECK-NEXT:    calll helper at PLT
+; CHECK-NEXT:    movl %esp, %ecx
+; CHECK-NEXT:    leal 31(,%eax,4), %eax
+; CHECK-NEXT:    andl $-32, %eax
+; CHECK-NEXT:    movl %ecx, %edx
+; CHECK-NEXT:    subl %eax, %edx
+; CHECK-NEXT:    movl %edx, %esp
+; CHECK-NEXT:    negl %eax
+; CHECK-NEXT:    movl $0, (%ecx,%eax)
+; CHECK-NEXT:    leal -4(%ebp), %esp
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    popl %ebp
+; CHECK-NEXT:    retl
+entry:
+  %k = call i32 @helper()
+  %a = alloca i32, i32 %k, align 4
+  store i32 0, ptr %a, align 4
+  ret void
+}
+
+define void @clobber_base() #0 {
+; CHECK-LABEL: clobber_base:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %ebp
+; CHECK-NEXT:    movl %esp, %ebp
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    andl $-128, %esp
+; CHECK-NEXT:    subl $128, %esp
+; CHECK-NEXT:    movl %esp, %esi
+; CHECK-NEXT:    calll helper at PLT
+; CHECK-NEXT:    movl %esp, %ecx
+; CHECK-NEXT:    leal 31(,%eax,4), %eax
+; CHECK-NEXT:    andl $-32, %eax
+; CHECK-NEXT:    movl %ecx, %edx
+; CHECK-NEXT:    subl %eax, %edx
+; CHECK-NEXT:    movl %edx, %esp
+; CHECK-NEXT:    negl %eax
+; CHECK-NEXT:    movl $405, %esi # imm = 0x195
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    movl $8, %edx
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    movl %edx, (%esi)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    movl $0, (%ecx,%eax)
+; CHECK-NEXT:    leal -4(%ebp), %esp
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    popl %ebp
+; CHECK-NEXT:    retl
+entry:
+  %k = call i32 @helper()
+  %a = alloca i32, align 128
+  %b = alloca i32, i32 %k, align 4
+  ; clobber base pointer register
+  tail call void asm sideeffect "nop", "{si}"(i32 405)
+  call void asm sideeffect "movl $0, $1", "r,*m"(i32 8, ptr elementtype(i32) %a)
+  store i32 0, ptr %b, align 4
+  ret void
+}
+
+attributes #0 = { nounwind "frame-pointer"="all"}
+!llvm.module.flags = !{!0}
+!0 = !{i32 2, !"override-stack-alignment", i32 32}

diff  --git a/llvm/test/CodeGen/X86/x86-64-baseptr.ll b/llvm/test/CodeGen/X86/x86-64-baseptr.ll
index 161be485e47fa..decf1f0e437ec 100644
--- a/llvm/test/CodeGen/X86/x86-64-baseptr.ll
+++ b/llvm/test/CodeGen/X86/x86-64-baseptr.ll
@@ -64,6 +64,79 @@ entry:
   ret void
 }
 
+define void @clobber_base() #0 {
+; CHECK-LABEL: clobber_base:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rbp
+; CHECK-NEXT:    movq %rsp, %rbp
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    andq $-128, %rsp
+; CHECK-NEXT:    subq $128, %rsp
+; CHECK-NEXT:    movq %rsp, %rbx
+; CHECK-NEXT:    callq helper at PLT
+; CHECK-NEXT:    movq %rsp, %rcx
+; CHECK-NEXT:    movl %eax, %eax
+; CHECK-NEXT:    leaq 31(,%rax,4), %rax
+; CHECK-NEXT:    andq $-32, %rax
+; CHECK-NEXT:    movq %rcx, %rdx
+; CHECK-NEXT:    subq %rax, %rdx
+; CHECK-NEXT:    movq %rdx, %rsp
+; CHECK-NEXT:    negq %rax
+; CHECK-NEXT:    movl $405, %ebx # imm = 0x195
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    movl $8, %edx
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    movl %edx, (%rbx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    movl $0, (%rcx,%rax)
+; CHECK-NEXT:    leaq -8(%rbp), %rsp
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    popq %rbp
+; CHECK-NEXT:    retq
+;
+; X32ABI-LABEL: clobber_base:
+; X32ABI:       # %bb.0: # %entry
+; X32ABI-NEXT:    pushq %rbp
+; X32ABI-NEXT:    movl %esp, %ebp
+; X32ABI-NEXT:    pushq %rbx
+; X32ABI-NEXT:    andl $-128, %esp
+; X32ABI-NEXT:    subl $128, %esp
+; X32ABI-NEXT:    movl %esp, %ebx
+; X32ABI-NEXT:    callq helper at PLT
+; X32ABI-NEXT:    # kill: def $eax killed $eax def $rax
+; X32ABI-NEXT:    leal 31(,%rax,4), %eax
+; X32ABI-NEXT:    andl $-32, %eax
+; X32ABI-NEXT:    movl %esp, %ecx
+; X32ABI-NEXT:    movl %ecx, %edx
+; X32ABI-NEXT:    subl %eax, %edx
+; X32ABI-NEXT:    negl %eax
+; X32ABI-NEXT:    movl %edx, %esp
+; X32ABI-NEXT:    movl $405, %ebx # imm = 0x195
+; X32ABI-NEXT:    #APP
+; X32ABI-NEXT:    nop
+; X32ABI-NEXT:    #NO_APP
+; X32ABI-NEXT:    movl $8, %edx
+; X32ABI-NEXT:    #APP
+; X32ABI-NEXT:    movl %edx, (%ebx)
+; X32ABI-NEXT:    #NO_APP
+; X32ABI-NEXT:    movl $0, (%ecx,%eax)
+; X32ABI-NEXT:    leal -8(%ebp), %esp
+; X32ABI-NEXT:    popq %rbx
+; X32ABI-NEXT:    popq %rbp
+; X32ABI-NEXT:    retq
+entry:
+  %k = call i32 @helper()
+  %a = alloca i32, align 128
+  %b = alloca i32, i32 %k, align 4
+  ; clobber base pointer register
+  tail call void asm sideeffect "nop", "{bx}"(i32 405)
+  call void asm sideeffect "movl $0, $1", "r,*m"(i32 8, ptr elementtype(i32) %a)
+  store i32 0, ptr %b, align 4
+  ret void
+}
+
 attributes #0 = { nounwind "frame-pointer"="all"}
 !llvm.module.flags = !{!0}
 !0 = !{i32 2, !"override-stack-alignment", i32 32}