[PATCH] D144116: [DAGCombiner] Avoid converting (x or/xor const) + y to (x + y) + const if benefit is unclear

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2667
           isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true)) {
-        return DAG.getNode(ISD::ADD, DL, VT,
-                           DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(0)),
-                           N0.getOperand(1));
+        bool NoAddCarry = TLI.isOperationLegal(ISD::ADD, N0.getValueType());
+        ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N0.getOperand(1));
----------------
aqjune wrote:
> RKSimon wrote:
> > Just because the ADD isn't legal doesn't mean we're going to end up with ADC instructions
> Could you elaborate a bit about this please?
> If it means that a legal ADD can still be splitted into a chain of ADDS/ADCS/ADC, is there a way to find the bitwidth of addition that will not be splitted?
I think TLI.getTypeToExpandTo should help you ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144116/new/

https://reviews.llvm.org/D144116