[PATCH] D144412: [NFC] Fix missing colon in CHECK directives

[Shivam Gupta via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbfb1559fbe2f: [NFC] Fix missing colon in CHECK directives (authored by aabhinavg, committed by xgupta).

Changed prior to commit:
  https://reviews.llvm.org/D144412?vs=498889&id=498907#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144412/new/

https://reviews.llvm.org/D144412

Files:
  llvm/test/Analysis/MemorySSA/phi-translation.ll
  llvm/test/CodeGen/AArch64/kcfi-patchable-function-prefix.ll
  llvm/test/CodeGen/AMDGPU/fneg-combines.ll
  llvm/test/CodeGen/DirectX/strip-fn-attrs.ll
  llvm/test/Transforms/FunctionSpecialization/specialization-order.ll
  llvm/test/Transforms/InstCombine/2008-01-06-VoidCast.ll
  llvm/test/Transforms/LoopStrengthReduce/remove_scev_indvars.ll


Index: llvm/test/Transforms/LoopStrengthReduce/remove_scev_indvars.ll
===================================================================
--- llvm/test/Transforms/LoopStrengthReduce/remove_scev_indvars.ll
+++ llvm/test/Transforms/LoopStrengthReduce/remove_scev_indvars.ll
@@ -16,7 +16,7 @@
 
 ; CHECK: entry:
 ; CHECK: %0 = add i64 %n, %m
-; CHECK-NOT : %indvars.iv.next.prol
+; CHECK-NOT: %indvars.iv.next.prol
 ; CHECK-NOT: %indvars.iv.prol
 ; CHECK: %indvars.iv.unr = phi i64 [ %0, %for.exit ]
 for.exit:
Index: llvm/test/Transforms/InstCombine/2008-01-06-VoidCast.ll
===================================================================
--- llvm/test/Transforms/InstCombine/2008-01-06-VoidCast.ll
+++ llvm/test/Transforms/InstCombine/2008-01-06-VoidCast.ll
@@ -6,7 +6,7 @@
 
 define i32 @g(i32 %y) {
 ; CHECK-LABEL: @g(
-; CHECK-NEXT %x = call i32 @f(i32 %y)		; <i32> [#uses=1]
+; CHECK-NEXT: %x = call i32 @f(i32 %y)		; <i32> [#uses=1]
   %x = call i32 @f( i32 %y )		; <i32> [#uses=1]
   ret i32 %x
 }
Index: llvm/test/Transforms/FunctionSpecialization/specialization-order.ll
===================================================================
--- llvm/test/Transforms/FunctionSpecialization/specialization-order.ll
+++ llvm/test/Transforms/FunctionSpecialization/specialization-order.ll
@@ -37,8 +37,8 @@
 }
 
 define dso_local i32 @g2(i32 %x, i32 %y, ptr %v) {
-; CHECK-LABEL @g2
-; CHECK       call i32 @f.1(i32 [[X:%.*]], i32 [[Y:%.*]], ptr [[V:%.*]])
+; CHECK-LABEL: @g2
+; CHECK:       call i32 @f.1(i32 [[X:%.*]], i32 [[Y:%.*]], ptr [[V:%.*]])
 entry:
   %call = tail call i32 @f(i32 %x, i32 %y, ptr @sub, ptr %v)
   ret i32 %call
@@ -54,5 +54,5 @@
 
 ; CHECK-LABEL: define {{.*}} i32 @f.3
 ; CHECK:       call i32 @add(i32 %x, i32 %y)
-; CHECK-NEXT   call i32 @add(i32 %x, i32 %y)
+; CHECK-NEXT:   call i32 @add(i32 %x, i32 %y)
 
Index: llvm/test/CodeGen/DirectX/strip-fn-attrs.ll
===================================================================
--- llvm/test/CodeGen/DirectX/strip-fn-attrs.ll
+++ llvm/test/CodeGen/DirectX/strip-fn-attrs.ll
@@ -14,7 +14,7 @@
 declare void @llvm.dbg.value(metadata, metadata, metadata) #1
 
 ; CHECK: attributes #0 = { nounwind memory(none) }
-; CHECK-NOT attributes #
+; CHECK-NOT: attributes #
 
 attributes #0 = { norecurse nounwind readnone willreturn }
 attributes #1 = { nofree nosync nounwind readnone speculatable willreturn }
Index: llvm/test/CodeGen/AMDGPU/fneg-combines.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/fneg-combines.ll
+++ llvm/test/CodeGen/AMDGPU/fneg-combines.ll
@@ -569,7 +569,7 @@
 
 ; GCN-LABEL: {{^}}v_fneg_0_minnum_f32:
 ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
-; GCN-NOT [[A]]
+; GCN-NOT: [[A]]
 ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], 0, [[A]]
 ; GCN: v_xor_b32_e32 [[RESULT:v[0-9]+]], 0x80000000, [[MIN]]
 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
Index: llvm/test/CodeGen/AArch64/kcfi-patchable-function-prefix.ll
===================================================================
--- llvm/test/CodeGen/AArch64/kcfi-patchable-function-prefix.ll
+++ llvm/test/CodeGen/AArch64/kcfi-patchable-function-prefix.ll
@@ -11,7 +11,7 @@
 }
 
 ; CHECK:          .p2align 2
-; CHECK-NOT       .word
+; CHECK-NOT:       .word
 ; CHECK-NOT:        nop
 ; CHECK-LABEL:    f2:
 define void @f2(ptr noundef %x) {
Index: llvm/test/Analysis/MemorySSA/phi-translation.ll
===================================================================
--- llvm/test/Analysis/MemorySSA/phi-translation.ll
+++ llvm/test/Analysis/MemorySSA/phi-translation.ll
@@ -432,7 +432,7 @@
 
 ; CHECK-LABEL: merge:
 ; CHECK:       ; 3 = MemoryPhi({lhs,1},{rhs,2})
-; CHECK-NEXT   %storemerge2 = phi i32 [ 2, %lhs ], [ 3, %rhs ]
+; CHECK-NEXT:   %storemerge2 = phi i32 [ 2, %lhs ], [ 3, %rhs ]
 ; LIMIT:       ; MemoryUse(3)
 ; LIMIT-NEXT:  %lv = load i16, ptr %arrayidx, align 2
 ; NOLIMIT:     ; MemoryUse(liveOnEntry)


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