[PATCH] D144143: [RISCV] Improve isInterleaveShuffle to handle interleaving the high half and low half of the same source.

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll:12
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e16, mf4, ta, ma
 ; CHECK-NEXT:    vwaddu.vv v10, v8, v9
----------------
@craig.topper Are these VLs double than what's necessary?

```
v10: v2f32 = vmaddu.vv v8: v2f16, v9: v2f16 
SEW = e16
v10 EEW = e32
VL needed = 2

v10: v2f32 = vwmaccu.vx v10: v2f32, a0, v9: v2f16 
SEW = e16
v10 EEW = e32
VL needed = 2
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144143/new/

https://reviews.llvm.org/D144143