[PATCH] D144034: [AMDGPU][GFX11] Legalize and select partial NSA MIMG instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Do we need verifier checks for the NSA restrictions on gfx11?



================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:1863
+  const bool UseNSA =
+      NumVAddrRegs != 1 && (IsGFX11Plus ? NumVAddrDwords >= NumVAddrRegs
+                                        : NumVAddrDwords == NumVAddrRegs);
----------------
Add a comment to explain there's a limit on gfx11


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:4985
+  const unsigned NSAMaxSize = ST.getNSAMaxSize();
+  const bool IsGFX11Plus = AMDGPU::isGFX11Plus(ST);
+
----------------
Can you make the descriptive of the NSA behavior rather than check/refer to gfx11+?


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:5001
+
+      if (PartialNSA && PackedRegs.size() > NSAMaxSize) {
+        LLT PackedAddrTy =
----------------
Comment that this is packing the last register?


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:4639
         VAddrWords = SRsrcIdx - VAddr0Idx;
+        if (ST.getGeneration() >= AMDGPUSubtarget::GFX11 && AddrWords > 5) {
+          unsigned LastVAddrIdx = SRsrcIdx - 1;
----------------
Avoid generation check?


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:4643
+          VAddrWords +=
+              MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 32 - 1;
+        }
----------------
This is just RI.getRegSizeInBits


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  https://reviews.llvm.org/D144034/new/

https://reviews.llvm.org/D144034