[PATCH] D144313: [AMDGPU] Improve the lowering of raw_buffer_load_{i8,i16} and struct_buffer_load_{i8,i16} intrinsics
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 20 04:02:43 PST 2023
arsenm added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp:391
+ Register Op0Reg = MI.getOperand(1).getReg();
+ MachineInstr *SubwordBufferLoad = (*(MRI.def_begin(Op0Reg))).getParent();
+ Register SignExtendInsnDst = MI.getOperand(0).getReg();
----------------
getVRegDef?
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp:393
+ Register SignExtendInsnDst = MI.getOperand(0).getReg();
+ B.setInsertPt(*(MI.getParent()), MI);
+
----------------
The calling combiner code should really set the insert point for you, not sure why we still don't do that
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144313/new/
https://reviews.llvm.org/D144313
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