[PATCH] D141560: [RISCV][CodeGen] Add codegen pattern for experimental zfa extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1476
+
+  if (Subtarget.hasStdExtZfa()) {
+    if (VT == MVT::f32 && RISCVLoadFPImm::getLoadFP32Imm(Imm) == -1)
----------------
This needs to be rebased.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td:177
+
+def bitcast_fp32imm_to_loadfpimm : SDNodeXForm<fpimm, [{
+  return CurDAG->getTargetConstant(RISCVLoadFPImm::getLoadFP32Imm(N->getValueAPF()), 
----------------
This isn't a "bitcast". It's an encoding conversion.

fpimm is now handled with custom code in RISCVISelDAGToDAG.cpp so this needs to be moved there.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141560/new/

https://reviews.llvm.org/D141560