[PATCH] D143838: [X86] Improve (select carry C1+1 C1)

[Kazu Hirata via Phabricator via llvm-commits]

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Without this patch:

  return X < 4 ? 3 : 2;
  
  return X < 9 ? 7 : 6;

are compiled as:

  31 c0                   xor    %eax,%eax
  83 ff 04                cmp    $0x4,%edi
  0f 93 c0                setae  %al
  83 f0 03                xor    $0x3,%eax
  
  31 c0                   xor    %eax,%eax
  83 ff 09                cmp    $0x9,%edi
  0f 92 c0                setb   %al
  83 c8 06                or     $0x6,%eax

respectively.  With this patch, we generate:

  31 c0                   xor    %eax,%eax
  83 ff 04                cmp    $0x4,%edi
  83 d0 02                adc    $0x2,%eax
  
  31 c0                   xor    %eax,%eax
  83 ff 04                cmp    $0x4,%edi
  83 d0 02                adc    $0x2,%eax

respectively, saving 3 bytes while reducing the tree height.

This patch recognizes the equivalence of OR and ADD
(if bits do not overlap) and delegates to combineAddOrSubToADCOrSBB
for further processing.  The same applies to the equivalence of XOR
and SUB.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143838

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/select_const.ll

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