[PATCH] D142254: [X86] Transform vector SET{LE/ULT/ULE} -> SETLT and SET{GE/UGT/UGE} -> SETGT if possible

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Sorry - I kept missing this - just a couple of minors.

For some reason I thought there were more targets with limited condcodes.



================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:53280
+/// NOTE: The element count check is to ignore operand types that need to
+/// go through type promotion to a 128-bit vector.
+static SDValue truncateAVX512SetCCNoBWI(EVT VT, EVT OpVT, SDValue LHS,
----------------
This NOTE mentions a count check - but there isn't one?


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:53412
+  if (VT.isVector() && OpVT.isVector()) {
+    if (OpVT.getVectorElementType().isScalarInteger()) {
+      bool CanMakeSigned = false;
----------------
Why not just OpVT.isInteger()?


Repository:
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  https://reviews.llvm.org/D142254/new/

https://reviews.llvm.org/D142254