[PATCH] D142132: [AArch64] Map DestructiveTernaryCommWithRev intrinsics to pesudo instructions

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Hi @lizhijin, I don't think this patch makes much sense because at the code generation layer we already have pseudo instructions to allow better FMLA/FMAD usage based on what the register allocate chooses to do. I suspect the problem you care about is due to how the C/C++ builtins are lowered for things like `svmla_x`? which currently overly restricts code generation.  I've created a patch series that ends with D143767 <https://reviews.llvm.org/D143767> that I believe fulfils the intent of what you wanted to achieve. Please let me know if I've misunderstood the issue you wanted to solve.

NOTE: D143767 <https://reviews.llvm.org/D143767> can be extend to integer MLAs but there's ongoing work on the code generation side (D142656 <https://reviews.llvm.org/D142656>) before that can be done.


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  https://reviews.llvm.org/D142132/new/

https://reviews.llvm.org/D142132