[PATCH] D143757: [AMDGPU] Enable predicated copy right from instruction selection
Christudasan Devadasan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 10 09:26:39 PST 2023
cdevadas created this revision.
cdevadas added reviewers: arsenm, rampitec.
Herald added subscribers: kosarev, foad, wenlei, kerbowa, arphaman, kbarton, hiraditya, tpr, dstuttard, yaxunl, jvesely, nemanjai, kzhuravl, qcolombet, MatzeB.
Herald added a project: All.
cdevadas requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.
This patch would enable the predicated copy opcode by default
for AMDGPU right from the instruction selection. At certain
point after regalloc, they will be fixed. When for SGPR copies
they become regular COPY opcodes, for all vector copies, the
implicit exec use will be added still retaining the PRED_COPY
opcode. Based on the register class involved, later `copyPhysReg`
called during expand post-RA pseudos will lower all forms of
copy opcodes into respective target instructions.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D143757
Files:
llvm/lib/Target/AMDGPU/AMDGPU.h
llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/lib/Target/AMDGPU/CMakeLists.txt
llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
llvm/lib/Target/AMDGPU/SISimplifyPredicatedCopies.cpp
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
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