[PATCH] D143754: [MachineInstr] Introduce generic predicated copy opcode

[Christudasan Devadasan via Phabricator via llvm-commits]

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The copy operation with a predicated dependency is currently
marked with an implicit operand. It is good to have a separate
opcode for such instances to distinguish them from the regular
copies that have no dependencies at all. This will allow targets
more control while lowering the copies. AMDGPU, for instance,
have the implicit dependency with exec register for all vector
copies and no such dependency for scalar copies and there is a
custom pass currently adds the implicit exec operand to every
vector copy and that doesn't look right.

This patch introduces a new opcode PRED_COPY, called the
predicated equivalent of the existing COPY opcode. Targets
can define the default copy opcode and the `getCopyOpcode`
callback would return the chosen opcode appropriately. Every
interface that needs `TargetOpcode::COPY` should now be replaced
with a call to `getCopyOpcode`. Targets have the control over how
and when to lower the PRED_COPY instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143754

Files:
  llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
  llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
  llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
  llvm/include/llvm/CodeGen/MachineInstr.h
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/GlobalISel/Combine.td
  llvm/include/llvm/Target/Target.td
  llvm/lib/CodeGen/CodeGenCommonISel.cpp
  llvm/lib/CodeGen/DetectDeadLanes.cpp
  llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
  llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
  llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
  llvm/lib/CodeGen/GlobalISel/Utils.cpp
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/lib/CodeGen/PeepholeOptimizer.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/CodeGen/SplitKit.cpp
  llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  llvm/lib/CodeGen/VLIWMachineScheduler.cpp
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedA64FX.td
  llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
  llvm/lib/Target/AArch64/AArch64SchedTSV110.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AMDGPU/SISchedule.td
  llvm/lib/Target/AMDGPU/VOP3Instructions.td
  llvm/lib/Target/ARM/ARMScheduleA57.td
  llvm/lib/Target/ARM/ARMScheduleM4.td
  llvm/lib/Target/ARM/ARMScheduleR52.td
  llvm/lib/Target/Mips/MipsScheduleGeneric.td
  llvm/lib/Target/Mips/MipsScheduleP5600.td
  llvm/lib/Target/PowerPC/P10InstrResources.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/RISCV/RISCVSchedRocket.td
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
  llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
  llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
  llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
  llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
  llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
  llvm/lib/Target/X86/X86SchedBroadwell.td
  llvm/lib/Target/X86/X86SchedSandyBridge.td
  llvm/lib/Target/X86/X86ScheduleAtom.td
  llvm/lib/Target/X86/X86ScheduleBdVer2.td
  llvm/lib/Target/X86/X86ScheduleSLM.td
  llvm/lib/Target/X86/X86ScheduleZnver1.td
  llvm/lib/Target/X86/X86ScheduleZnver2.td
  llvm/lib/Target/X86/X86ScheduleZnver3.td
  llvm/utils/TableGen/InstrInfoEmitter.cpp

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