[llvm] c4ce967 - ARM: skip debug instructions when matching jump-table patterns.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 10 04:28:07 PST 2023
Author: Tim Northover
Date: 2023-02-10T12:27:59Z
New Revision: c4ce967e3437864827fe8e8816c2a8993b4d796b
URL: https://github.com/llvm/llvm-project/commit/c4ce967e3437864827fe8e8816c2a8993b4d796b
DIFF: https://github.com/llvm/llvm-project/commit/c4ce967e3437864827fe8e8816c2a8993b4d796b.diff
LOG: ARM: skip debug instructions when matching jump-table patterns.
When working out whether we can see a compressible jump-table pattern during
ConstantIslands, we were stopping when we saw a debug instruction. Instead it's
better to keep iterating backwards to the first real instruction.
https://reviews.llvm.org/D142019
Added:
llvm/test/CodeGen/ARM/jump-table-dbg-value.mir
Modified:
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index 386a74877bc17..0fa7258ad1edf 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -2278,9 +2278,12 @@ bool ARMConstantIslands::optimizeThumb2JumpTables() {
// %t = tLDRr %base, %idx
Register BaseReg = User.MI->getOperand(0).getReg();
- if (User.MI->getIterator() == User.MI->getParent()->begin())
+ MachineBasicBlock *UserMBB = User.MI->getParent();
+ MachineBasicBlock::iterator Shift = User.MI->getIterator();
+ if (Shift == UserMBB->begin())
continue;
- MachineInstr *Shift = User.MI->getPrevNode();
+
+ Shift = prev_nodbg(Shift, UserMBB->begin());
if (Shift->getOpcode() != ARM::tLSLri ||
Shift->getOperand(3).getImm() != 2 ||
!Shift->getOperand(2).isKill())
diff --git a/llvm/test/CodeGen/ARM/jump-table-dbg-value.mir b/llvm/test/CodeGen/ARM/jump-table-dbg-value.mir
new file mode 100644
index 0000000000000..413f5ef52929b
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/jump-table-dbg-value.mir
@@ -0,0 +1,160 @@
+# RUN: llc -mtriple=thumbv6m-apple-unknown-macho --run-pass=arm-cp-islands -o - %s | FileCheck %s
+--- |
+ ; ModuleID = 'test.ll'
+ source_filename = "simple.ll"
+ target datalayout = "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv6m-apple-unknown-macho"
+
+ define i32 @foo(i32 %in) !dbg !5 {
+ call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
+ switch i32 %in, label %default [
+ i32 0, label %l0
+ i32 1, label %l1
+ i32 2, label %l2
+ i32 3, label %l3
+ ], !dbg !11
+
+ default: ; preds = %0
+ ret i32 42, !dbg !12
+
+ l0: ; preds = %0
+ ret i32 0, !dbg !13
+
+ l1: ; preds = %0
+ ret i32 1, !dbg !14
+
+ l2: ; preds = %0
+ ret i32 2, !dbg !15
+
+ l3: ; preds = %0
+ ret i32 3, !dbg !16
+ }
+
+ ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+ declare void @llvm.dbg.value(metadata, metadata, metadata) #0
+
+ attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+
+ !llvm.dbg.cu = !{!0}
+ !llvm.debugify = !{!2, !3}
+ !llvm.module.flags = !{!4}
+
+ !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
+ !1 = !DIFile(filename: "simple.ll", directory: "/")
+ !2 = !{i32 6}
+ !3 = !{i32 1}
+ !4 = !{i32 2, !"Debug Info Version", i32 3}
+ !5 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8)
+ !6 = !DISubroutineType(types: !7)
+ !7 = !{}
+ !8 = !{!9}
+ !9 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 1, type: !10)
+ !10 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned)
+ !11 = !DILocation(line: 1, column: 1, scope: !5)
+ !12 = !DILocation(line: 2, column: 1, scope: !5)
+ !13 = !DILocation(line: 3, column: 1, scope: !5)
+ !14 = !DILocation(line: 4, column: 1, scope: !5)
+ !15 = !DILocation(line: 5, column: 1, scope: !5)
+ !16 = !DILocation(line: 6, column: 1, scope: !5)
+
+...
+---
+name: foo
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+callsEHReturn: false
+callsUnwindInit: false
+hasEHCatchret: false
+hasEHScopes: false
+hasEHFunclets: false
+debugInstrRef: false
+failsVerification: false
+tracksDebugUserValues: true
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ functionContext: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ hasTailCall: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack: []
+callSites: []
+debugValueSubstitutions: []
+constants: []
+machineFunctionInfo: {}
+jumpTable:
+ kind: inline
+ entries:
+ - id: 0
+ blocks: [ '%bb.3', '%bb.4', '%bb.5', '%bb.6' ]
+body: |
+ bb.0 (%ir-block.0):
+ successors: %bb.2(0x19999998), %bb.1(0x66666668)
+ liveins: $r0
+
+ DBG_VALUE 0, $noreg, !9, !DIExpression(), debug-location !11
+ tCMPi8 renamable $r0, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !11
+ tBcc %bb.2, 8 /* CC::hi */, killed $cpsr, debug-location !11
+
+ bb.1 (%ir-block.0):
+ successors: %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000), %bb.6(0x20000000)
+ liveins: $r0
+
+ renamable $r0, dead $cpsr = tLSLri killed renamable $r0, 2, 14 /* CC::al */, $noreg
+ DBG_VALUE 0, $noreg, !9, !DIExpression(), debug-location !11
+ renamable $r1 = tLEApcrelJT %jump-table.0, 14 /* CC::al */, $noreg
+ renamable $r0 = tLDRr renamable $r1, killed renamable $r0, 14 /* CC::al */, $noreg :: (load (s32) from jump-table)
+ renamable $r0, dead $cpsr = tADDrr killed renamable $r1, killed renamable $r0, 14 /* CC::al */, $noreg
+ tBR_JTr killed renamable $r0, %jump-table.0
+ ; CHECK: tTBB_JT
+
+ bb.3.l0:
+ DBG_VALUE 0, $noreg, !9, !DIExpression(), debug-location !11
+ renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0, debug-location !13
+
+ bb.2.default:
+ DBG_VALUE 0, $noreg, !9, !DIExpression(), debug-location !11
+ renamable $r0, dead $cpsr = tMOVi8 42, 14 /* CC::al */, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0, debug-location !12
+
+ bb.4.l1:
+ DBG_VALUE 0, $noreg, !9, !DIExpression(), debug-location !11
+ renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0, debug-location !14
+
+ bb.5.l2:
+ DBG_VALUE 0, $noreg, !9, !DIExpression(), debug-location !11
+ renamable $r0, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0, debug-location !15
+
+ bb.6.l3:
+ DBG_VALUE 0, $noreg, !9, !DIExpression(), debug-location !11
+ renamable $r0, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0, debug-location !16
+
+...
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