[PATCH] D143707: [AMDGPU] Allow architected SGPRs for workgroup IDs
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 10 04:10:02 PST 2023
foad added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:2254
assert(!Subtarget->hasUserSGPRInit16Bug() || IsShader ||
Info.getNumPreloadedSGPRs() >= 16);
}
----------------
cdevadas wrote:
> Also, should I guard this check with HasArchitectedSGPRS?
> The numPreloaded regular SGPRs will vary if TTMP registers are used for workgroup IDs.
@arsenm?
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Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:707
+ Register Reg = HasArchitectedSGPRs ? AMDGPU::TTMP7 : getNextSystemSGPR();
+ unsigned Mask = HasArchitectedSGPRs && hasWorkGroupIDZ() ? 0xffff : ~0u;
+ ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(Reg, Mask);
----------------
cdevadas wrote:
> The hasWorkGroupIDZ() will be set to 1 if there is a workgroup IDZ used. Otherwise, this function would return false.
> The WorkGroupIDX, WorkGroupIDY, and WorkGroupIDZ fields in the MachineFunctionInfo would have set/reset it by now.
>
OK, I understand now, if the function does not call @llvm.amdgcn.workgroup.id.z then the compiler will not set COMPUTE_PGM_RSRC2:TGID_Z_EN so the hardware will initialize the top half of TTMP7 to 0.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D143707/new/
https://reviews.llvm.org/D143707
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