[llvm] f0f8ae7 - [AMDGPU][AsmParser] Fix matching immediate literals.

[Ivan Kosarev via llvm-commits]

Author: Ivan Kosarev
Date: 2023-02-10T11:36:07Z
New Revision: f0f8ae7596c458349f92ccea61519013245b6c3c

URL: https://github.com/llvm/llvm-project/commit/f0f8ae7596c458349f92ccea61519013245b6c3c
DIFF: https://github.com/llvm/llvm-project/commit/f0f8ae7596c458349f92ccea61519013245b6c3c.diff

LOG: [AMDGPU][AsmParser] Fix matching immediate literals.

Prevents potential matching of literal offsets to non-literal operands.

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D142194

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    llvm/test/MC/AMDGPU/gfx7_err_pos.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index e3a70866e2e8e..ceb83655117fe 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -347,6 +347,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
     return isImm() && Imm.Type == ImmT;
   }
 
+  bool isImmLiteral() const { return isImmTy(ImmTyNone); }
+
   bool isImmModifier() const {
     return isImm() && Imm.Type != ImmTyNone;
   }
@@ -7940,7 +7942,7 @@ void AMDGPUAsmParser::cvtIntersectRay(MCInst &Inst,
 //===----------------------------------------------------------------------===//
 
 bool AMDGPUOperand::isSMRDOffset8() const {
-  return isImm() && isUInt<8>(getImm());
+  return isImmLiteral() && isUInt<8>(getImm());
 }
 
 bool AMDGPUOperand::isSMEMOffset() const {
@@ -7951,7 +7953,7 @@ bool AMDGPUOperand::isSMEMOffset() const {
 bool AMDGPUOperand::isSMRDLiteralOffset() const {
   // 32-bit literals are only supported on CI and we only want to use them
   // when the offset is > 8-bits.
-  return isImm() && !isUInt<8>(getImm()) && isUInt<32>(getImm());
+  return isImmLiteral() && !isUInt<8>(getImm()) && isUInt<32>(getImm());
 }
 
 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDOffset8() const {
@@ -8439,11 +8441,11 @@ bool AMDGPUOperand::isABID() const {
 }
 
 bool AMDGPUOperand::isS16Imm() const {
-  return isImm() && (isInt<16>(getImm()) || isUInt<16>(getImm()));
+  return isImmLiteral() && (isInt<16>(getImm()) || isUInt<16>(getImm()));
 }
 
 bool AMDGPUOperand::isU16Imm() const {
-  return isImm() && isUInt<16>(getImm());
+  return isImmLiteral() && isUInt<16>(getImm());
 }
 
 //===----------------------------------------------------------------------===//

diff  --git a/llvm/test/MC/AMDGPU/gfx7_err_pos.s b/llvm/test/MC/AMDGPU/gfx7_err_pos.s
index 7799052fa3d62..b9473a26e62a5 100644
--- a/llvm/test/MC/AMDGPU/gfx7_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx7_err_pos.s
@@ -36,3 +36,11 @@ v_and_b32_e64 v0, 0.159154943091895317852646485335, v1
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: literal operands are not supported
 // CHECK-NEXT:{{^}}v_and_b32_e64 v0, 0.159154943091895317852646485335, v1
 // CHECK-NEXT:{{^}}                  ^
+
+//==============================================================================
+// cache policy is not supported for SMRD instructions
+
+s_load_dword s5, s[2:3], glc
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: cache policy is not supported for SMRD instructions
+// CHECK-NEXT:{{^}}s_load_dword s5, s[2:3], glc
+// CHECK-NEXT:{{^}}                         ^