[llvm] 393675d - [Test] Add test showing an opportunity to transform checks and hoist invariants
Max Kazantsev via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 10 02:45:44 PST 2023
Author: Max Kazantsev
Date: 2023-02-10T17:42:16+07:00
New Revision: 393675dad0c0eb66c759ec47cb1e3e7fe5ff8fcf
URL: https://github.com/llvm/llvm-project/commit/393675dad0c0eb66c759ec47cb1e3e7fe5ff8fcf
DIFF: https://github.com/llvm/llvm-project/commit/393675dad0c0eb66c759ec47cb1e3e7fe5ff8fcf.diff
LOG: [Test] Add test showing an opportunity to transform checks and hoist invariants
Added:
llvm/test/Transforms/LoopInstSimplify/loop_invariant.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LoopInstSimplify/loop_invariant.ll b/llvm/test/Transforms/LoopInstSimplify/loop_invariant.ll
new file mode 100644
index 0000000000000..728db6f67fb9f
--- /dev/null
+++ b/llvm/test/Transforms/LoopInstSimplify/loop_invariant.ll
@@ -0,0 +1,251 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S %s -passes=loop-instsimplify | FileCheck %s
+; RUN: opt -S %s -passes='loop-mssa(loop-instsimplify)' -verify-memoryssa | FileCheck %s
+
+; TODO: turn to %iv <u umin(inv_1, inv_2) and hoist it out of loop.
+define i32 @test_ult(i32 %start, i32 %inv_1, i32 %inv_2) {
+; CHECK-LABEL: @test_ult(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[CMP_1:%.*]] = icmp ult i32 [[IV]], [[INV_1:%.*]]
+; CHECK-NEXT: [[CMP_2:%.*]] = icmp ult i32 [[IV]], [[INV_2:%.*]]
+; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[IV_LCSSA]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [%start, %entry], [%iv.next, %loop]
+ %cmp_1 = icmp ult i32 %iv, %inv_1
+ %cmp_2 = icmp ult i32 %iv, %inv_2
+ %loop_cond = and i1 %cmp_1, %cmp_2
+ %iv.next = add i32 %iv, 1
+ br i1 %loop_cond, label %loop, label %exit
+
+exit:
+ ret i32 %iv
+}
+
+; TODO: turn to %iv <=u umin(inv_1, inv_2) and hoist it out of loop.
+define i32 @test_ule(i32 %start, i32 %inv_1, i32 %inv_2) {
+; CHECK-LABEL: @test_ule(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[CMP_1:%.*]] = icmp ule i32 [[IV]], [[INV_1:%.*]]
+; CHECK-NEXT: [[CMP_2:%.*]] = icmp ule i32 [[IV]], [[INV_2:%.*]]
+; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[IV_LCSSA]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [%start, %entry], [%iv.next, %loop]
+ %cmp_1 = icmp ule i32 %iv, %inv_1
+ %cmp_2 = icmp ule i32 %iv, %inv_2
+ %loop_cond = and i1 %cmp_1, %cmp_2
+ %iv.next = add i32 %iv, 1
+ br i1 %loop_cond, label %loop, label %exit
+
+exit:
+ ret i32 %iv
+}
+
+; TODO: turn to %iv <s smin(inv_1, inv_2) and hoist it out of loop.
+define i32 @test_slt(i32 %start, i32 %inv_1, i32 %inv_2) {
+; CHECK-LABEL: @test_slt(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[CMP_1:%.*]] = icmp slt i32 [[IV]], [[INV_1:%.*]]
+; CHECK-NEXT: [[CMP_2:%.*]] = icmp slt i32 [[IV]], [[INV_2:%.*]]
+; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[IV_LCSSA]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [%start, %entry], [%iv.next, %loop]
+ %cmp_1 = icmp slt i32 %iv, %inv_1
+ %cmp_2 = icmp slt i32 %iv, %inv_2
+ %loop_cond = and i1 %cmp_1, %cmp_2
+ %iv.next = add i32 %iv, 1
+ br i1 %loop_cond, label %loop, label %exit
+
+exit:
+ ret i32 %iv
+}
+
+; TODO: turn to %iv <=s smin(inv_1, inv_2) and hoist it out of loop.
+define i32 @test_sle(i32 %start, i32 %inv_1, i32 %inv_2) {
+; CHECK-LABEL: @test_sle(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[CMP_1:%.*]] = icmp sle i32 [[IV]], [[INV_1:%.*]]
+; CHECK-NEXT: [[CMP_2:%.*]] = icmp sle i32 [[IV]], [[INV_2:%.*]]
+; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[IV_LCSSA]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [%start, %entry], [%iv.next, %loop]
+ %cmp_1 = icmp sle i32 %iv, %inv_1
+ %cmp_2 = icmp sle i32 %iv, %inv_2
+ %loop_cond = and i1 %cmp_1, %cmp_2
+ %iv.next = add i32 %iv, 1
+ br i1 %loop_cond, label %loop, label %exit
+
+exit:
+ ret i32 %iv
+}
+
+; TODO: turn to %iv >u umax(inv_1, inv_2) and hoist it out of loop.
+define i32 @test_ugt(i32 %start, i32 %inv_1, i32 %inv_2) {
+; CHECK-LABEL: @test_ugt(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[CMP_1:%.*]] = icmp ugt i32 [[IV]], [[INV_1:%.*]]
+; CHECK-NEXT: [[CMP_2:%.*]] = icmp ugt i32 [[IV]], [[INV_2:%.*]]
+; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[IV_LCSSA]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [%start, %entry], [%iv.next, %loop]
+ %cmp_1 = icmp ugt i32 %iv, %inv_1
+ %cmp_2 = icmp ugt i32 %iv, %inv_2
+ %loop_cond = and i1 %cmp_1, %cmp_2
+ %iv.next = add i32 %iv, 1
+ br i1 %loop_cond, label %loop, label %exit
+
+exit:
+ ret i32 %iv
+}
+
+; TODO: turn to %iv >=u umax(inv_1, inv_2) and hoist it out of loop.
+define i32 @test_uge(i32 %start, i32 %inv_1, i32 %inv_2) {
+; CHECK-LABEL: @test_uge(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[CMP_1:%.*]] = icmp uge i32 [[IV]], [[INV_1:%.*]]
+; CHECK-NEXT: [[CMP_2:%.*]] = icmp uge i32 [[IV]], [[INV_2:%.*]]
+; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[IV_LCSSA]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [%start, %entry], [%iv.next, %loop]
+ %cmp_1 = icmp uge i32 %iv, %inv_1
+ %cmp_2 = icmp uge i32 %iv, %inv_2
+ %loop_cond = and i1 %cmp_1, %cmp_2
+ %iv.next = add i32 %iv, 1
+ br i1 %loop_cond, label %loop, label %exit
+
+exit:
+ ret i32 %iv
+}
+
+; TODO: turn to %iv >s smax(inv_1, inv_2) and hoist it out of loop.
+define i32 @test_sgt(i32 %start, i32 %inv_1, i32 %inv_2) {
+; CHECK-LABEL: @test_sgt(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[CMP_1:%.*]] = icmp sgt i32 [[IV]], [[INV_1:%.*]]
+; CHECK-NEXT: [[CMP_2:%.*]] = icmp sgt i32 [[IV]], [[INV_2:%.*]]
+; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[IV_LCSSA]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [%start, %entry], [%iv.next, %loop]
+ %cmp_1 = icmp sgt i32 %iv, %inv_1
+ %cmp_2 = icmp sgt i32 %iv, %inv_2
+ %loop_cond = and i1 %cmp_1, %cmp_2
+ %iv.next = add i32 %iv, 1
+ br i1 %loop_cond, label %loop, label %exit
+
+exit:
+ ret i32 %iv
+}
+
+; TODO: turn to %iv >=s smax(inv_1, inv_2) and hoist it out of loop.
+define i32 @test_sge(i32 %start, i32 %inv_1, i32 %inv_2) {
+; CHECK-LABEL: @test_sge(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
+; CHECK-NEXT: [[CMP_1:%.*]] = icmp sge i32 [[IV]], [[INV_1:%.*]]
+; CHECK-NEXT: [[CMP_2:%.*]] = icmp sge i32 [[IV]], [[INV_2:%.*]]
+; CHECK-NEXT: [[LOOP_COND:%.*]] = and i1 [[CMP_1]], [[CMP_2]]
+; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
+; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
+; CHECK: exit:
+; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i32 [ [[IV]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[IV_LCSSA]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i32 [%start, %entry], [%iv.next, %loop]
+ %cmp_1 = icmp sge i32 %iv, %inv_1
+ %cmp_2 = icmp sge i32 %iv, %inv_2
+ %loop_cond = and i1 %cmp_1, %cmp_2
+ %iv.next = add i32 %iv, 1
+ br i1 %loop_cond, label %loop, label %exit
+
+exit:
+ ret i32 %iv
+}
More information about the llvm-commits
mailing list