[PATCH] D143069: [DAGCombine] Allow DAGCombine to remove dead masked stores

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Thanks for adding the tests @dtemirbulatov! I've just got two more nits on the tests, then I'm happy to accept.



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Comment at: llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll:36-37
+  %alltrue = shufflevector  <vscale x 4 x i1> %alltrue.ins,  <vscale x 4 x i1> poison,  <vscale x 4 x i32> zeroinitializer
+  call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)
+  call void @llvm.masked.store.nxv4i64(<vscale x 4 x i64> %val1, ptr %a, i32 4, <vscale x 4 x i1> %alltrue)
+  ret void
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Can you change this to:

  call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)
  call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val1, ptr %a, i32 4, <vscale x 4 x i1> %mask) ; with same value for the mask

such that it's more clear that the first store is eliminated?

Now it code-generates the store of nxv4i64 into two stores, because nxv4i64 is not a legal type and needs splitting.



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Comment at: llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll:51
+  call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)
+  call void @llvm.masked.store.nxv4i16(<vscale x 4 x i16> %val1, ptr %a, i32 4, <vscale x 4 x i1> %alltrue)
+  ret void
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For this test, can you use the same %mask value?


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  https://reviews.llvm.org/D143069/new/

https://reviews.llvm.org/D143069