[PATCH] D143619: [llvm][codegen] Disallow default Emulated TLS for RISCV
Vitaly Cheptsov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 10 00:00:51 PST 2023
vit9696 requested changes to this revision.
vit9696 added a comment.
This revision now requires changes to proceed.
This change looks inadequate to me. As I explicitly stated in the mentioned issue <https://github.com/llvm/llvm-project/issues/59500#issuecomment-1349012654>, we need emutls support for RISC-V. For the reasons stated there I believe we should enable emutls support for RISC-V as GCC does, and this differential should be abandoned.
Just to clarify, emutls support is literally as simple as adding these three lines:
diff -rupN a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 2022-06-22 19:46:24
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 2022-12-14 11:48:02
@@ -3718,6 +3718,9 @@ SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDV
SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
SelectionDAG &DAG) const {
+ GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
+ if (DAG.getTarget().useEmulatedTLS())
+ return LowerToTLSEmulatedModel(GA, DAG);
SDLoc DL(Op);
EVT Ty = Op.getValueType();
GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D143619/new/
https://reviews.llvm.org/D143619
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