[PATCH] D143076: [RISCV] Implement a proposed mapping for Ztso

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3735
     return DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
-
   return Op;
----------------
Was this whitespace change intentional?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3736
+    if (FenceOrdering == AtomicOrdering::SequentiallyConsistent &&
+        FenceSSID == SyncScope::System) {
+      return Op;
----------------
Drop curly braces


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143076/new/

https://reviews.llvm.org/D143076