[PATCH] D143439: [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:318
+    if (Subtarget.is64Bit())
+      setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
+  }
----------------
philipp.tomsich wrote:
> craig.topper wrote:
> > without these two lines to promote i32, I suppose we would get zext i32 to i64, ff1, addi? Is the sequence used for ctlzw better than that?
> The sequences will have an identical critical-path (and require the same number of temporaries).
> I read your comment as a recommendation to simplify the overall implementation (by removing the special case here and in the pattern-matching).
Yes that would be my recommendation if there's no reason to prefer one over the other.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143439/new/

https://reviews.llvm.org/D143439