[PATCH] D136861: [IR] Add LLVM IR support for target("aarch64.svcount") type.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Thanks for all the previous comments! I've rewritten the patch to use the new target-extension types, since that functionality has now landed. This made the patch a lot simpler. I've only had to add a new interface to check if the TargetExtType is scalable.

I will try to be a bit more responsive to comments this time around :)

In D136861#3900512 <https://reviews.llvm.org/D136861#3900512>, @efriedma wrote:

> From the spec, `svreinterpret_c(svreinterpret_b(x))` is equivalent to x, right?  So you could just lower svcount_t to `<vscale x 16 x i1>`, but you want to avoid confusion with non-SME predicate vectors in LLVM IR?

We could let Clang emit the reinterpret cast, but we want the intrinsics to be correct for other front-ends as well think of e.g. MLIR. By giving it a proper type it becomes unambiguous what the format of the predicate value must be when passing it to the intrinsic.


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