[PATCH] D143570: [RISCV][MC] Add support for RV64E

Wed Feb 8 21:11:32 PST 2023

jrtc27 added inline comments.

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Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:499
+                        AssemblerPredicate<(all_of FeatureRVE)>;

 def FeatureRelax
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pcwang-thead wrote:
> pcwang-thead wrote:
> > How about this?
> > ```
> > def IsRVE : Predicate<"Subtarget->isRVE()">,
> >                         AssemblerPredicate<(all_of FeatureRVE)>;
> > def IsRV32E : Predicate<"Subtarget->is32RVE()">,
> >                         AssemblerPredicate<(all_of FeatureRVE, Feature32Bit)>;
> > def IsRV64E : Predicate<"Subtarget->is64RVE()">,
> >                        AssemblerPredicate<(all_of FeatureRVE, Feature64Bit)>;
> > ```
> Oops, I mean `Subtarget->isRV32E()` and `Subtarget->isRV64E()`.
Why do you need that? Just use IsRV32/64 and IsRVE as appropriate. We don't have IsRV32F, IsRV64D, IsRV32A, etc.

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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:78-81
+  if (Subtarget.isRVE() && !Subtarget.is64Bit())
     report_fatal_error("Codegen not yet implemented for RV32E");
+  if (Subtarget.isRVE() && Subtarget.is64Bit())
+    report_fatal_error("Codegen not yet implemented for RV64E");
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They'll surely come together, just change the error message to RVE?

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143570/new/

https://reviews.llvm.org/D143570