[PATCH] D142071: [RISCV] Enable preferZeroCompareBranch to optimize branch on zero in codegenprepare

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added a comment.

If we want to solve this regression for @optbranch_64, we need to lowering ISD::ADDCARRY and ISD::SETCCCARRY.

But I checked these nodes all used for carry bit/flags. For rv64gc/rv32gc we do not have instructions to handle carry-add or carry-sub.

Maybe this lowering can be used in rvv.  They have `11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions`

So I will create a patch for TLI->shouldFormOverflowOp.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D142071/new/

https://reviews.llvm.org/D142071