[PATCH] D143014: [InstCombine] Add combines for `(urem/srem (mul/shl X, Y), (mul/shl X, Z))`
Noah Goldstein via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 8 12:06:25 PST 2023
goldstein.w.n added inline comments.
================
Comment at: llvm/test/Transforms/InstCombine/urem-mul.ll:41
}
define i8 @urem_XY_XZ_with_CY_rem_CZ_eq_0_fail_missing_flag(i8 %X) {
----------------
MattDevereau wrote:
> It would be good to have a positive test case where both sides of the rem are shl binops
We have `@urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_with_nsw_out2`
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D143014/new/
https://reviews.llvm.org/D143014
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