[PATCH] D143276: [SME2][AArch64] Add multi-single multiply-add long long intrinsics

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2757
 
-multiclass sme2_mla_ll_array_vg24_single<string mnemonic, bits<5> op,
+multiclass sme2_mla_ll_array_vg2_single<string mnemonic, bits<5> op,
+                                          MatrixOperand matrix_ty,
----------------
This is just a suggestion, but in theory you could reduce the amount of duplication by creating a multiclass sme2_mla_ll_array_vg24_single like this:

  multiclass sme2_mla_ll_array_vg24_single<string mnemonic, bits<5> op,
                                          MatrixOperand matrix_ty,
                                          RegisterOperand multi_vector_ty,
                                          ZPRRegOp zpr_ty, ValueType vt, SDPatternOperator intrinsic> {
    def NAME: sme2_mla_ll_array_vg24_single<op, matrix_ty, multi_vector_ty,
                                          zpr_ty, mnemonic>, SMEPseudo2Instr<NAME, 1>;

    def NAME # _PSEUDO : sme2_za_array_2op_multi_single_pseudo<NAME, uimm1s4range, multi_vector_ty, zpr_ty, SMEMatrixArray>;

    def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm], $Zn, $Zm",
                   (!cast<Instruction>(NAME) matrix_ty:$ZAd,  MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm, multi_vector_ty:$Zn, zpr_ty:$Zm), 0>;
  }

Then for each of vg2 and vg4 you just need:

  multiclass sme2_mla_ll_array_vg2_single<string mnemonic, bits<5> op,
                                          MatrixOperand matrix_ty,
                                          RegisterOperand multi_vector_ty,
                                          ZPRRegOp zpr_ty, ValueType vt, SDPatternOperator intrinsic> {
    defm : sme2_mla_ll_array_vg24_single;

    def : SME2_ZA_TwoOp_VG2_Multi_Single_Pat<NAME, intrinsic, uimm1s4range, zpr_ty, vt, tileslicerange1s4>;
  }

Please feel free to ignore this suggestion if you think it doesn't improve things. I wouldn't hold up the patch for it!


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Comment at: llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+sme2 -mattr=+sme-i16i64 -verify-machineinstrs < %s | FileCheck %s
+
----------------
nit: I don't think we need the `-mattr=+sve` flag here, since sme2 implies it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143276/new/

https://reviews.llvm.org/D143276