[PATCH] D143574: AMDGPU/MC: Fix decoders for VSrc_v2b32 and VSrc_v2f32 RegisterOperands

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Petar.Avramovic added a reviewer: dp.
Herald added subscribers: kosarev, foad, kerbowa, hiraditya, tpr, dstuttard, yaxunl, jvesely, kzhuravl, arsenm.
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Decoder should make 32 bit value when decoding immediates, not 64 bit.


https://reviews.llvm.org/D143574

Files:
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/test/MC/Disassembler/AMDGPU/gfx90a_features.txt


Index: llvm/test/MC/Disassembler/AMDGPU/gfx90a_features.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/gfx90a_features.txt
+++ llvm/test/MC/Disassembler/AMDGPU/gfx90a_features.txt
@@ -51,7 +51,7 @@
 # GFX90A: v_pk_fma_f32 v[0:1], v[4:5], v[8:9], v[16:17] ; encoding: [0x00,0x40,0xb0,0xd3,0x04,0x11,0x42,0x1c]
 0x00,0x40,0xb0,0xd3,0x04,0x11,0x42,0x1c
 
-# GFX90A: v_pk_fma_f32 v[0:1], v[2:3], v[4:5], 0  ; encoding: [0x00,0x40,0xb0,0xd3,0x02,0x09,0x02,0x1a]
+# GFX90A: v_pk_fma_f32 v[0:1], v[2:3], v[4:5], 1.0 ; encoding: [0x00,0x40,0xb0,0xd3,0x02,0x09,0xca,0x1b]
 0x00,0x40,0xb0,0xd3,0x02,0x09,0xca,0x1b
 
 # GFX90A: v_pk_mul_f32 v[254:255], v[8:9], v[16:17] ; encoding: [0xfe,0x40,0xb1,0xd3,0x08,0x21,0x02,0x18]
@@ -138,7 +138,7 @@
 # GFX90A: v_pk_mul_f32 v[4:5], v[8:9], v[16:17] clamp ; encoding: [0x04,0xc0,0xb1,0xd3,0x08,0x21,0x02,0x18]
 0x04,0x80,0xb1,0xd3,0x08,0x21,0x02,0x18
 
-# GFX90A: v_pk_mul_f32 v[0:1], v[2:3], 0 ; encoding: [0x00,0x40,0xb1,0xd3,0x02,0x01,0x01,0x18]
+# GFX90A: v_pk_mul_f32 v[0:1], v[2:3], 1.0 ; encoding: [0x00,0x40,0xb1,0xd3,0x02,0xe5,0x01,0x18]
 0x00,0x40,0xb1,0xd3,0x02,0xe5,0x01,0x18
 
 # GFX90A: v_pk_add_f32 v[254:255], v[8:9], v[16:17] ; encoding: [0xfe,0x40,0xb2,0xd3,0x08,0x21,0x02,0x18]
@@ -225,7 +225,7 @@
 # GFX90A: v_pk_add_f32 v[4:5], v[8:9], v[16:17] clamp ; encoding: [0x04,0xc0,0xb2,0xd3,0x08,0x21,0x02,0x18]
 0x04,0x80,0xb2,0xd3,0x08,0x21,0x02,0x18
 
-# GFX90A: v_pk_add_f32 v[0:1], v[2:3], 0 ; encoding: [0x00,0x40,0xb2,0xd3,0x02,0x01,0x01,0x18]
+# GFX90A: v_pk_add_f32 v[0:1], v[2:3], 1.0 ; encoding: [0x00,0x40,0xb2,0xd3,0x02,0xe5,0x01,0x18]
 0x00,0x40,0xb2,0xd3,0x02,0xe5,0x01,0x18
 
 # GFX90A: v_pk_mov_b32 v[0:1], v[2:3], v[4:5] ; encoding: [0x00,0x40,0xb3,0xd3,0x02,0x09,0x02,0x18]
@@ -252,7 +252,7 @@
 # GFX90A: v_pk_mov_b32 v[0:1], v[2:3], 4 ; encoding: [0x00,0x40,0xb3,0xd3,0x02,0x09,0x01,0x18]
 0x00,0x40,0xb3,0xd3,0x02,0x09,0x01,0x18
 
-# GFX90A: v_pk_mov_b32 v[0:1], v[2:3], 0 ; encoding: [0x00,0x40,0xb3,0xd3,0x02,0x01,0x01,0x18]
+# GFX90A: v_pk_mov_b32 v[0:1], v[2:3], 2.0 ; encoding: [0x00,0x40,0xb3,0xd3,0x02,0xe9,0x01,0x18]
 0x00,0x40,0xb3,0xd3,0x02,0xe9,0x01,0x18
 
 # GFX90A: buffer_wbl2 ; encoding: [0x00,0x00,0xa0,0xe0,0x00,0x00,0x00,0x00]
Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1109,11 +1109,11 @@
 
 class RegOrV2F32 <string RegisterClass, string OperandTypePrefix>
   : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2FP32",
-                     !subst("_v2f32", "V2FP32", NAME), "_Imm64">;
+                     !subst("_v2f32", "V2FP32", NAME), "_Imm32">;
 
 class RegOrV2B32 <string RegisterClass, string OperandTypePrefix>
   : RegOrImmOperand <RegisterClass, OperandTypePrefix # "_V2INT32",
-                     !subst("_v2b32", "V2INT32", NAME), "_Imm64">;
+                     !subst("_v2b32", "V2INT32", NAME), "_Imm32">;
 
 // For VOP1,2,C True16 instructions. _Lo128 use first 128 32-bit VGPRs only.
 class RegOrB16_Lo128 <string RegisterClass, string OperandTypePrefix>
Index: llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -245,6 +245,7 @@
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64)
+DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32)
 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64)


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