[PATCH] D143570: [RISCV][MC] Add support for RV64E

[Job Noorman via Phabricator via llvm-commits]

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Implement MC support for the recently ratified RV64E <https://drive.google.com/file/d/1GjHmphVKvJlOBJydAt36g0Oc8yCOPtKw/view?usp=share_link> base instruction set.

This patch does two things. First, it implements RV64E by trying to share as much code as possible with RV32E. This seems to make sense since the logic is exactly the same (restrict the available registers to x0-x15). However, it has some consequences that make me wonder if this is a good idea:

- the existing feature (`FeatureRV32E`) and predicate (`IsRV32E`) have been renamed to `FeatureRVE` and `IsRVE`. The acronym "RVE" might not be immediately clear to people;
- the RV128I base ISA doesn't currently define an equivalent RV128E variant. This is not a problem since LLVM doesn't implement it yet but we might have to reintroduce some checks this patch removes if it ever does.

Secondly, this patch introduces the recently proposed (but not yet ratified) lp64e ABI <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/299>. It doesn't do anything besides setting the `EF_RISCV_RVE` ELF flag and some consistency checking. I'm not sure whether it's acceptable to introduce such an unstable ABI so I can remove this part or move it to a separate revision if that's preferred.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143570

Files:
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
  llvm/test/CodeGen/RISCV/rv64e.ll
  llvm/test/MC/RISCV/elf-flags.s
  llvm/test/MC/RISCV/mattr-invalid-combination.s
  llvm/test/MC/RISCV/rv32e-invalid.s
  llvm/test/MC/RISCV/rv32e-valid.s
  llvm/test/MC/RISCV/rv64e-valid.s
  llvm/test/MC/RISCV/target-abi-invalid.s
  llvm/test/MC/RISCV/target-abi-valid.s

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