[PATCH] D141429: [AArch64] Codegen for FEAT_LRCPC3

Wed Feb 8 02:01:38 PST 2023

tmatheson added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-rcpc3.ll:283
+; CHECK:    ldp x1, x0, [x0]
+; CHECK:    dmb ish
     %r = load atomic i128, ptr %ptr seq_cst, align 16
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efriedma wrote:
> efriedma wrote:
> > Sort of orthogonal to this change, but can someone at ARM verify if this is the sequence we actually want for sequentially consistent loads with lse2, as opposed to using caspal?  (I'm a bit concerned given the issues we ran into with narrower widths on Windows; see D141748.)
> Any update here?
Not yet but I haven't forgotten about it.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141429/new/

https://reviews.llvm.org/D141429