[PATCH] D143448: [NVPTX] Lower extraction of upper half of i32/i64 as partial move.

[Artem Belevich via Phabricator via llvm-commits]

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This produces better SASS than right-shift + truncate and is fairly common for
CUDA code that operates on __half2 values represented as opaque integer.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143448

Files:
  llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
  llvm/test/CodeGen/NVPTX/f16-instructions.ll
  llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
  llvm/test/CodeGen/NVPTX/idioms.ll

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