[PATCH] D143036: [RISCV] Add vendor-defined XTHeadBs (single-bit) extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:970
+          // Also Skip if we can use bexti or th.tst.
           Skip |= Subtarget->hasStdExtZbs() && Leading == XLen - 1;
+          Skip |= Subtarget->hasVendorXTHeadBs() && Leading == XLen - 1;
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These two lines can be merged

`Skip |= HasBitTest && Leading == XLen - 1`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143036/new/

https://reviews.llvm.org/D143036