[llvm] d170a25 - [CodeGen] Define and use MachineOperand::getOperandNo
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 7 04:00:29 PST 2023
Author: Jay Foad
Date: 2023-02-07T11:50:57Z
New Revision: d170a254a53bce54596ed0f94aa86ffa3eede42b
URL: https://github.com/llvm/llvm-project/commit/d170a254a53bce54596ed0f94aa86ffa3eede42b
DIFF: https://github.com/llvm/llvm-project/commit/d170a254a53bce54596ed0f94aa86ffa3eede42b.diff
LOG: [CodeGen] Define and use MachineOperand::getOperandNo
This is a helper function to very slightly simplify many calls to
MachineInstruction::getOperandNo.
Differential Revision: https://reviews.llvm.org/D143250
Added:
Modified:
llvm/include/llvm/CodeGen/MachineOperand.h
llvm/lib/CodeGen/CalcSpillWeights.cpp
llvm/lib/CodeGen/DetectDeadLanes.cpp
llvm/lib/CodeGen/GlobalISel/Localizer.cpp
llvm/lib/CodeGen/LiveVariables.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/MachineOperand.cpp
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/lib/CodeGen/MachineSink.cpp
llvm/lib/CodeGen/MachineTraceMetrics.cpp
llvm/lib/CodeGen/RenameIndependentSubregs.cpp
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/lib/CodeGen/SplitKit.cpp
llvm/lib/CodeGen/StackMaps.cpp
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineOperand.h b/llvm/include/llvm/CodeGen/MachineOperand.h
index 75710a4542e48..1f3b7feedd189 100644
--- a/llvm/include/llvm/CodeGen/MachineOperand.h
+++ b/llvm/include/llvm/CodeGen/MachineOperand.h
@@ -253,6 +253,9 @@ class MachineOperand {
///
void clearParent() { ParentMI = nullptr; }
+ /// Returns the index of this operand in the instruction that it belongs to.
+ unsigned getOperandNo() const;
+
/// Print a subreg index operand.
/// MO_Immediate operands can also be subreg idices. If it's the case, the
/// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp
index 615687abad818..1146c1d465da5 100644
--- a/llvm/lib/CodeGen/CalcSpillWeights.cpp
+++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp
@@ -133,7 +133,7 @@ bool VirtRegAuxInfo::isLiveAtStatepointVarArg(LiveInterval &LI) {
MachineInstr *MI = MO.getParent();
if (MI->getOpcode() != TargetOpcode::STATEPOINT)
return false;
- return StatepointOpers(MI).getVarIdx() <= MI->getOperandNo(&MO);
+ return StatepointOpers(MI).getVarIdx() <= MO.getOperandNo();
});
}
diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp
index 86a62bd438dc3..9d3452c2e2977 100644
--- a/llvm/lib/CodeGen/DetectDeadLanes.cpp
+++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp
@@ -80,11 +80,11 @@ static bool isCrossCopy(const MachineRegisterInfo &MRI,
unsigned DstSubIdx = 0;
switch (MI.getOpcode()) {
case TargetOpcode::INSERT_SUBREG:
- if (MI.getOperandNo(&MO) == 2)
+ if (MO.getOperandNo() == 2)
DstSubIdx = MI.getOperand(3).getImm();
break;
case TargetOpcode::REG_SEQUENCE: {
- unsigned OpNum = MI.getOperandNo(&MO);
+ unsigned OpNum = MO.getOperandNo();
DstSubIdx = MI.getOperand(OpNum+1).getImm();
break;
}
@@ -145,7 +145,7 @@ LaneBitmask
DeadLaneDetector::transferUsedLanes(const MachineInstr &MI,
LaneBitmask UsedLanes,
const MachineOperand &MO) const {
- unsigned OpNum = MI.getOperandNo(&MO);
+ unsigned OpNum = MO.getOperandNo();
assert(lowersToCopies(MI) &&
DefinedByCopy[Register::virtReg2Index(MI.getOperand(0).getReg())]);
@@ -208,7 +208,7 @@ void DeadLaneDetector::transferDefinedLanesStep(const MachineOperand &Use,
if (!DefinedByCopy.test(DefRegIdx))
return;
- unsigned OpNum = MI.getOperandNo(&Use);
+ unsigned OpNum = Use.getOperandNo();
DefinedLanes =
TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes);
@@ -317,7 +317,7 @@ LaneBitmask DeadLaneDetector::determineInitialDefinedLanes(unsigned Reg) {
MOSubReg, MODefinedLanes);
}
- unsigned OpNum = DefMI.getOperandNo(&MO);
+ unsigned OpNum = MO.getOperandNo();
DefinedLanes |= transferDefinedLanes(Def, OpNum, MODefinedLanes);
}
return DefinedLanes;
diff --git a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp
index bf4dcc2c24596..55984423e5bc6 100644
--- a/llvm/lib/CodeGen/GlobalISel/Localizer.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Localizer.cpp
@@ -54,7 +54,7 @@ bool Localizer::isLocalUse(MachineOperand &MOUse, const MachineInstr &Def,
MachineInstr &MIUse = *MOUse.getParent();
InsertMBB = MIUse.getParent();
if (MIUse.isPHI())
- InsertMBB = MIUse.getOperand(MIUse.getOperandNo(&MOUse) + 1).getMBB();
+ InsertMBB = MIUse.getOperand(MOUse.getOperandNo() + 1).getMBB();
return InsertMBB == Def.getParent();
}
@@ -99,7 +99,7 @@ bool Localizer::localizeInterBlock(MachineFunction &MF,
MachineBasicBlock *InsertMBB;
LLVM_DEBUG(MachineInstr &MIUse = *MOUse.getParent();
dbgs() << "Checking use: " << MIUse
- << " #Opd: " << MIUse.getOperandNo(&MOUse) << '\n');
+ << " #Opd: " << MOUse.getOperandNo() << '\n');
if (isLocalUse(MOUse, MI, InsertMBB)) {
// Even if we're in the same block, if the block is very large we could
// still have many long live ranges. Try to do intra-block localization
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 34c81c92707e2..547e9a9443af3 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -699,7 +699,7 @@ void LiveVariables::recomputeForSingleDefVirtReg(Register Reg) {
if (UseMI.isPHI()) {
// If Reg is used in a phi then it is live-to-end of the corresponding
// predecessor.
- unsigned Idx = UseMI.getOperandNo(&UseMO);
+ unsigned Idx = UseMO.getOperandNo();
LiveToEndBlocks.push_back(UseMI.getOperand(Idx + 1).getMBB());
} else if (&UseBB == &DefBB) {
// A non-phi use in the same BB as the single def must come after the def.
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index 243587394463c..a0e20437fbf37 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -1086,8 +1086,7 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
for (auto &MO : Inst->operands()) {
if (!MO.isReg() || !MO.isDef() || MO.getReg() != State.first)
continue;
- return ApplySubregisters(
- {Inst->getDebugInstrNum(), Inst->getOperandNo(&MO)});
+ return ApplySubregisters({Inst->getDebugInstrNum(), MO.getOperandNo()});
}
llvm_unreachable("Vreg def with no corresponding operand?");
@@ -1109,7 +1108,7 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
continue;
return ApplySubregisters(
- {ToExamine.getDebugInstrNum(), ToExamine.getOperandNo(&MO)});
+ {ToExamine.getDebugInstrNum(), MO.getOperandNo()});
}
}
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 0a7b12e9ccb9c..1178a93961054 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -53,6 +53,11 @@ static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
}
+unsigned MachineOperand::getOperandNo() const {
+ assert(getParent() && "Operand does not belong to any instruction!");
+ return getParent()->getOperandNo(this);
+}
+
void MachineOperand::setReg(Register Reg) {
if (getReg() == Reg)
return; // No change.
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index adb6304690034..772b77e93c325 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -865,13 +865,11 @@ void SwingSchedulerDAG::updatePhiDependences() {
unsigned HasPhiDef = 0;
MachineInstr *MI = I.getInstr();
// Iterate over each operand, and we process the definitions.
- for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
- MOE = MI->operands_end();
- MOI != MOE; ++MOI) {
- if (!MOI->isReg())
+ for (const MachineOperand &MO : MI->operands()) {
+ if (!MO.isReg())
continue;
- Register Reg = MOI->getReg();
- if (MOI->isDef()) {
+ Register Reg = MO.getReg();
+ if (MO.isDef()) {
// If the register is used by a Phi, then create an anti dependence.
for (MachineRegisterInfo::use_instr_iterator
UI = MRI.use_instr_begin(Reg),
@@ -893,7 +891,7 @@ void SwingSchedulerDAG::updatePhiDependences() {
}
}
}
- } else if (MOI->isUse()) {
+ } else if (MO.isUse()) {
// If the register is defined by a Phi, then create a true dependence.
MachineInstr *DefMI = MRI.getUniqueVRegDef(Reg);
if (DefMI == nullptr)
@@ -903,7 +901,7 @@ void SwingSchedulerDAG::updatePhiDependences() {
if (!MI->isPHI()) {
SDep Dep(SU, SDep::Data, Reg);
Dep.setLatency(0);
- ST.adjustSchedDependency(SU, 0, &I, MI->getOperandNo(MOI), Dep);
+ ST.adjustSchedDependency(SU, 0, &I, MO.getOperandNo(), Dep);
I.addPred(Dep);
} else {
HasPhiUse = Reg;
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 8429d468254a9..f730dbd58dc60 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -331,7 +331,7 @@ bool MachineSinking::AllUsesDominatedByBlock(Register Reg,
// %p = PHI %y, %bb.0, %def, %bb.1
if (all_of(MRI->use_nodbg_operands(Reg), [&](MachineOperand &MO) {
MachineInstr *UseInst = MO.getParent();
- unsigned OpNo = UseInst->getOperandNo(&MO);
+ unsigned OpNo = MO.getOperandNo();
MachineBasicBlock *UseBlock = UseInst->getParent();
return UseBlock == MBB && UseInst->isPHI() &&
UseInst->getOperand(OpNo + 1).getMBB() == DefMBB;
diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
index 5c6efd4af0744..8f793a00ca472 100644
--- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp
+++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
@@ -655,9 +655,7 @@ static bool getDataDeps(const MachineInstr &UseMI,
return false;
bool HasPhysRegs = false;
- for (MachineInstr::const_mop_iterator I = UseMI.operands_begin(),
- E = UseMI.operands_end(); I != E; ++I) {
- const MachineOperand &MO = *I;
+ for (const MachineOperand &MO : UseMI.operands()) {
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
@@ -669,7 +667,7 @@ static bool getDataDeps(const MachineInstr &UseMI,
}
// Collect virtual register reads.
if (MO.readsReg())
- Deps.push_back(DataDep(MRI, Reg, UseMI.getOperandNo(I)));
+ Deps.push_back(DataDep(MRI, Reg, MO.getOperandNo()));
}
return HasPhysRegs;
}
@@ -703,9 +701,7 @@ static void updatePhysDepsDownwards(const MachineInstr *UseMI,
SmallVector<MCRegister, 8> Kills;
SmallVector<unsigned, 8> LiveDefOps;
- for (MachineInstr::const_mop_iterator MI = UseMI->operands_begin(),
- ME = UseMI->operands_end(); MI != ME; ++MI) {
- const MachineOperand &MO = *MI;
+ for (const MachineOperand &MO : UseMI->operands()) {
if (!MO.isReg() || !MO.getReg().isPhysical())
continue;
MCRegister Reg = MO.getReg().asMCReg();
@@ -714,7 +710,7 @@ static void updatePhysDepsDownwards(const MachineInstr *UseMI,
if (MO.isDead())
Kills.push_back(Reg);
else
- LiveDefOps.push_back(UseMI->getOperandNo(MI));
+ LiveDefOps.push_back(MO.getOperandNo());
} else if (MO.isKill())
Kills.push_back(Reg);
// Identify dependencies.
@@ -724,7 +720,7 @@ static void updatePhysDepsDownwards(const MachineInstr *UseMI,
SparseSet<LiveRegUnit>::iterator I = RegUnits.find(*Units);
if (I == RegUnits.end())
continue;
- Deps.push_back(DataDep(I->MI, I->Op, UseMI->getOperandNo(MI)));
+ Deps.push_back(DataDep(I->MI, I->Op, MO.getOperandNo()));
break;
}
}
@@ -895,17 +891,14 @@ static unsigned updatePhysDepsUpwards(const MachineInstr &MI, unsigned Height,
const TargetRegisterInfo *TRI) {
SmallVector<unsigned, 8> ReadOps;
- for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
- MOE = MI.operands_end();
- MOI != MOE; ++MOI) {
- const MachineOperand &MO = *MOI;
+ for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg())
continue;
Register Reg = MO.getReg();
if (!Reg.isPhysical())
continue;
if (MO.readsReg())
- ReadOps.push_back(MI.getOperandNo(MOI));
+ ReadOps.push_back(MO.getOperandNo());
if (!MO.isDef())
continue;
// This is a def of Reg. Remove corresponding entries from RegUnits, and
@@ -919,7 +912,7 @@ static unsigned updatePhysDepsUpwards(const MachineInstr &MI, unsigned Height,
if (!MI.isTransient()) {
// We may not know the UseMI of this dependency, if it came from the
// live-in list. SchedModel can handle a NULL UseMI.
- DepHeight += SchedModel.computeOperandLatency(&MI, MI.getOperandNo(MOI),
+ DepHeight += SchedModel.computeOperandLatency(&MI, MO.getOperandNo(),
I->MI, I->Op);
}
Height = std::max(Height, DepHeight);
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
index 05bbd1a2d03bf..71e214fc4dea2 100644
--- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
+++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
@@ -249,7 +249,7 @@ void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes,
/// Undef use operands are not tracked in the equivalence class,
/// but need to be updated if they are tied; take care to only
/// update the tied operand.
- unsigned OperandNo = MI->getOperandNo(&MO);
+ unsigned OperandNo = MO.getOperandNo();
unsigned TiedIdx = MI->findTiedOperandIdx(OperandNo);
MI->getOperand(TiedIdx).setReg(VReg);
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 1b213e87e75cf..6dcb1fac9a8ca 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -214,7 +214,7 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() {
if (Reg.isPhysical()) {
Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
} else if (Reg.isVirtual() && MO.readsReg()) {
- addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO));
+ addVRegUseDeps(&ExitSU, MO.getOperandNo());
}
}
}
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
index 92e820c9d3d82..eee54f09fbad0 100644
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -1365,7 +1365,7 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
// The point we want to extend is 0d to 16e not 16r in this case, but if
// we use 16r here we will extend nothing because that already contained
// in [16e, 32d).
- unsigned OpIdx = MI->getOperandNo(&MO);
+ unsigned OpIdx = MO.getOperandNo();
unsigned DefOpIdx = MI->findTiedOperandIdx(OpIdx);
const MachineOperand &DefOp = MI->getOperand(DefOpIdx);
IsEarlyClobber = DefOp.isEarlyClobber();
diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp
index bb7a51e49edb7..8f286c4a17bf4 100644
--- a/llvm/lib/CodeGen/StackMaps.cpp
+++ b/llvm/lib/CodeGen/StackMaps.cpp
@@ -149,7 +149,7 @@ unsigned StatepointOpers::getGCPointerMap(
bool StatepointOpers::isFoldableReg(Register Reg) const {
unsigned FoldableAreaStart = getVarIdx();
for (const MachineOperand &MO : MI->uses()) {
- if (MI->getOperandNo(&MO) >= FoldableAreaStart)
+ if (MO.getOperandNo() >= FoldableAreaStart)
break;
if (MO.isReg() && MO.getReg() == Reg)
return false;
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 8cb3667aea28a..8b0751f5e3d8f 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -404,7 +404,7 @@ findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB,
}
if (UseMI.isCommutable()) {
unsigned Src1 = TargetInstrInfo::CommuteAnyOperandIndex;
- unsigned Src2 = UseMI.getOperandNo(UseOp);
+ unsigned Src2 = UseOp->getOperandNo();
if (TII->findCommutedOpIndices(UseMI, Src1, Src2)) {
MachineOperand &MO = UseMI.getOperand(Src1);
if (MO.isReg() && MO.isUse() &&
@@ -693,10 +693,8 @@ bool TwoAddressInstructionPass::convertInstTo3Addr(
assert(NewMI->getNumExplicitDefs() == 1);
// Find the old and new def location.
- auto OldIt = mi->defs().begin();
- auto NewIt = NewMI->defs().begin();
- unsigned OldIdx = mi->getOperandNo(OldIt);
- unsigned NewIdx = NewMI->getOperandNo(NewIt);
+ unsigned OldIdx = mi->defs().begin()->getOperandNo();
+ unsigned NewIdx = NewMI->defs().begin()->getOperandNo();
// Record that one def has been replaced by the other.
unsigned NewInstrNum = NewMI->getDebugInstrNum();
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