[llvm] 7bff377 - [SDAG] Check fminnum/fmaxnum for non-zero operand.
Samuel Parker via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 7 02:54:58 PST 2023
Author: Samuel Parker
Date: 2023-02-07T10:54:23Z
New Revision: 7bff37783f72ed99e4cdd0fd7dad1bf1f119f793
URL: https://github.com/llvm/llvm-project/commit/7bff37783f72ed99e4cdd0fd7dad1bf1f119f793
DIFF: https://github.com/llvm/llvm-project/commit/7bff37783f72ed99e4cdd0fd7dad1bf1f119f793.diff
LOG: [SDAG] Check fminnum/fmaxnum for non-zero operand.
Currently, in TargetLowering, if the target does not support fminnum, we lower
to fminimum if neither operand could be a NaN. But this isn't quite correct
because fminnum and fminimum treat +/-0 differently; so, we need to prove that
one of the operands isn't a zero, or we don't have signed zeros.
Differential Revision: https://reviews.llvm.org/D143256
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/ARM/lower-vmax.ll
llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
llvm/test/CodeGen/WebAssembly/f32.ll
llvm/test/CodeGen/WebAssembly/f64.ll
llvm/test/CodeGen/WebAssembly/simd-arith.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index e26e70388c3a..051de2653809 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4918,9 +4918,21 @@ bool SelectionDAG::isKnownNeverZeroFloat(SDValue Op) const {
"Floating point type expected");
// If the value is a constant, we can obviously see if it is a zero or not.
- // TODO: Add BuildVector support.
if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op))
return !C->isZero();
+
+ // Return false if we find any zero in a vector.
+ if (Op->getOpcode() == ISD::BUILD_VECTOR ||
+ Op->getOpcode() == ISD::SPLAT_VECTOR) {
+ for (const SDValue &OpVal : Op->op_values()) {
+ if (OpVal.isUndef())
+ return false;
+ if (auto *C = dyn_cast<ConstantFPSDNode>(OpVal))
+ if (C->isZero())
+ return false;
+ }
+ return true;
+ }
return false;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index a990aeb17434..518970dfdf1f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -7985,14 +7985,17 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node,
}
// If the target has FMINIMUM/FMAXIMUM but not FMINNUM/FMAXNUM use that
- // instead if there are no NaNs.
- if (Node->getFlags().hasNoNaNs()) {
+ // instead if there are no NaNs and there can't be an incompatiable zero
+ // compare: at least one operand isn't +/-0, or there are no signed-zeros.
+ if (Node->getFlags().hasNoNaNs() &&
+ (Node->getFlags().hasNoSignedZeros() ||
+ DAG.isKnownNeverZeroFloat(Node->getOperand(0)) ||
+ DAG.isKnownNeverZeroFloat(Node->getOperand(1)))) {
unsigned IEEE2018Op =
Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM;
- if (isOperationLegalOrCustom(IEEE2018Op, VT)) {
+ if (isOperationLegalOrCustom(IEEE2018Op, VT))
return DAG.getNode(IEEE2018Op, dl, VT, Node->getOperand(0),
Node->getOperand(1), Node->getFlags());
- }
}
if (SDValue SelCC = createSelectForFMINNUM_FMAXNUM(Node, DAG))
diff --git a/llvm/test/CodeGen/ARM/lower-vmax.ll b/llvm/test/CodeGen/ARM/lower-vmax.ll
index ce96f449dbb0..73f0f165fdc7 100644
--- a/llvm/test/CodeGen/ARM/lower-vmax.ll
+++ b/llvm/test/CodeGen/ARM/lower-vmax.ll
@@ -1,11 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabihf -mattr=+neon < %s | FileCheck -check-prefixes=CHECK-NO_NEON %s
; RUN: llc -mtriple=arm-eabihf -mattr=+neon,+neonfp < %s | FileCheck -check-prefixes=CHECK-NEON %s
define float @max_f32(float, float) {
-;CHECK-NEON: vmax.f32
-;CHECK-NO_NEON: vcmp.f32
-;CHECK-NO_NEON: vmrs
-;CHECK-NO_NEON: vmovgt.f32
+; CHECK-NO_NEON-LABEL: max_f32:
+; CHECK-NO_NEON: @ %bb.0:
+; CHECK-NO_NEON-NEXT: vcmp.f32 s1, s0
+; CHECK-NO_NEON-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NO_NEON-NEXT: vmovgt.f32 s0, s1
+; CHECK-NO_NEON-NEXT: mov pc, lr
+;
+; CHECK-NEON-LABEL: max_f32:
+; CHECK-NEON: @ %bb.0:
+; CHECK-NEON-NEXT: vcmp.f32 s1, s0
+; CHECK-NEON-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEON-NEXT: vmovgt.f32 s0, s1
+; CHECK-NEON-NEXT: mov pc, lr
%3 = call nnan float @llvm.maxnum.f32(float %1, float %0)
ret float %3
}
@@ -13,10 +23,19 @@ define float @max_f32(float, float) {
declare float @llvm.maxnum.f32(float, float) #1
define float @min_f32(float, float) {
-;CHECK-NEON: vmin.f32
-;CHECK-NO_NEON: vcmp.f32
-;CHECK-NO_NEON: vmrs
-;CHECK-NO_NEON: vmovlt.f32
+; CHECK-NO_NEON-LABEL: min_f32:
+; CHECK-NO_NEON: @ %bb.0:
+; CHECK-NO_NEON-NEXT: vcmp.f32 s1, s0
+; CHECK-NO_NEON-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NO_NEON-NEXT: vmovlt.f32 s0, s1
+; CHECK-NO_NEON-NEXT: mov pc, lr
+;
+; CHECK-NEON-LABEL: min_f32:
+; CHECK-NEON: @ %bb.0:
+; CHECK-NEON-NEXT: vcmp.f32 s1, s0
+; CHECK-NEON-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEON-NEXT: vmovlt.f32 s0, s1
+; CHECK-NEON-NEXT: mov pc, lr
%3 = call nnan float @llvm.minnum.f32(float %1, float %0)
ret float %3
}
diff --git a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
index f21e22ca382f..e17075d067c2 100644
--- a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
@@ -502,13 +502,24 @@ define double @fmaxnum64_non_zero_intrinsic(double %x) {
define <4 x float> @fminnumv432_intrinsic(<4 x float> %x, <4 x float> %y) {
; ARMV7-LABEL: fminnumv432_intrinsic:
; ARMV7: @ %bb.0:
-; ARMV7-NEXT: vmov d17, r2, r3
-; ARMV7-NEXT: vmov d16, r0, r1
-; ARMV7-NEXT: mov r0, sp
-; ARMV7-NEXT: vld1.64 {d18, d19}, [r0]
-; ARMV7-NEXT: vmin.f32 q8, q8, q9
-; ARMV7-NEXT: vmov r0, r1, d16
-; ARMV7-NEXT: vmov r2, r3, d17
+; ARMV7-NEXT: mov r12, sp
+; ARMV7-NEXT: vld1.64 {d0, d1}, [r12]
+; ARMV7-NEXT: vmov d3, r2, r3
+; ARMV7-NEXT: vmov d2, r0, r1
+; ARMV7-NEXT: vcmp.f32 s7, s3
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vcmp.f32 s6, s2
+; ARMV7-NEXT: vmovlt.f32 s3, s7
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vcmp.f32 s5, s1
+; ARMV7-NEXT: vmovlt.f32 s2, s6
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vcmp.f32 s4, s0
+; ARMV7-NEXT: vmovlt.f32 s1, s5
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmovlt.f32 s0, s4
+; ARMV7-NEXT: vmov r2, r3, d1
+; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr
;
; ARMV8-LABEL: fminnumv432_intrinsic:
@@ -635,21 +646,31 @@ define <4 x float> @fminnumv432_non_zero_intrinsic(<4 x float> %x) {
define <4 x float> @fminnumv432_one_zero_intrinsic(<4 x float> %x) {
; ARMV7-LABEL: fminnumv432_one_zero_intrinsic:
; ARMV7: @ %bb.0:
-; ARMV7-NEXT: vmov d17, r2, r3
-; ARMV7-NEXT: vmov d16, r0, r1
-; ARMV7-NEXT: adr r0, .LCPI18_0
-; ARMV7-NEXT: vld1.64 {d18, d19}, [r0:128]
-; ARMV7-NEXT: vmin.f32 q8, q8, q9
-; ARMV7-NEXT: vmov r0, r1, d16
-; ARMV7-NEXT: vmov r2, r3, d17
+; ARMV7-NEXT: vmov d3, r2, r3
+; ARMV7-NEXT: vmov d2, r0, r1
+; ARMV7-NEXT: vmov.f32 s0, #-1.000000e+00
+; ARMV7-NEXT: vcmp.f32 s5, #0
+; ARMV7-NEXT: vldr s1, .LCPI18_0
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vcmp.f32 s7, s0
+; ARMV7-NEXT: vmovlt.f32 s1, s5
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmov.f32 s3, s0
+; ARMV7-NEXT: vcmp.f32 s6, s0
+; ARMV7-NEXT: vmovlt.f32 s3, s7
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmov.f32 s2, s0
+; ARMV7-NEXT: vcmp.f32 s4, s0
+; ARMV7-NEXT: vmovlt.f32 s2, s6
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmovlt.f32 s0, s4
+; ARMV7-NEXT: vmov r2, r3, d1
+; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr
-; ARMV7-NEXT: .p2align 4
+; ARMV7-NEXT: .p2align 2
; ARMV7-NEXT: @ %bb.1:
; ARMV7-NEXT: .LCPI18_0:
-; ARMV7-NEXT: .long 0xbf800000 @ float -1
; ARMV7-NEXT: .long 0x00000000 @ float 0
-; ARMV7-NEXT: .long 0xbf800000 @ float -1
-; ARMV7-NEXT: .long 0xbf800000 @ float -1
;
; ARMV8-LABEL: fminnumv432_one_zero_intrinsic:
; ARMV8: @ %bb.0:
@@ -697,13 +718,24 @@ define <4 x float> @fminnumv432_one_zero_intrinsic(<4 x float> %x) {
define <4 x float> @fmaxnumv432_intrinsic(<4 x float> %x, <4 x float> %y) {
; ARMV7-LABEL: fmaxnumv432_intrinsic:
; ARMV7: @ %bb.0:
-; ARMV7-NEXT: vmov d17, r2, r3
-; ARMV7-NEXT: vmov d16, r0, r1
-; ARMV7-NEXT: mov r0, sp
-; ARMV7-NEXT: vld1.64 {d18, d19}, [r0]
-; ARMV7-NEXT: vmax.f32 q8, q8, q9
-; ARMV7-NEXT: vmov r0, r1, d16
-; ARMV7-NEXT: vmov r2, r3, d17
+; ARMV7-NEXT: mov r12, sp
+; ARMV7-NEXT: vld1.64 {d0, d1}, [r12]
+; ARMV7-NEXT: vmov d3, r2, r3
+; ARMV7-NEXT: vmov d2, r0, r1
+; ARMV7-NEXT: vcmp.f32 s7, s3
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vcmp.f32 s6, s2
+; ARMV7-NEXT: vmovgt.f32 s3, s7
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vcmp.f32 s5, s1
+; ARMV7-NEXT: vmovgt.f32 s2, s6
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vcmp.f32 s4, s0
+; ARMV7-NEXT: vmovgt.f32 s1, s5
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmovgt.f32 s0, s4
+; ARMV7-NEXT: vmov r2, r3, d1
+; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr
;
; ARMV8-LABEL: fmaxnumv432_intrinsic:
@@ -789,13 +821,31 @@ define <4 x float> @fmaxnumv432_nsz_intrinsic(<4 x float> %x, <4 x float> %y) {
define <4 x float> @fmaxnumv432_zero_intrinsic(<4 x float> %x) {
; ARMV7-LABEL: fmaxnumv432_zero_intrinsic:
; ARMV7: @ %bb.0:
-; ARMV7-NEXT: vmov d19, r2, r3
-; ARMV7-NEXT: vmov.i32 q8, #0x0
-; ARMV7-NEXT: vmov d18, r0, r1
-; ARMV7-NEXT: vmax.f32 q8, q9, q8
-; ARMV7-NEXT: vmov r0, r1, d16
-; ARMV7-NEXT: vmov r2, r3, d17
+; ARMV7-NEXT: vmov d3, r2, r3
+; ARMV7-NEXT: vldr s0, .LCPI21_0
+; ARMV7-NEXT: vmov d2, r0, r1
+; ARMV7-NEXT: vcmp.f32 s7, #0
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmov.f32 s3, s0
+; ARMV7-NEXT: vcmp.f32 s6, #0
+; ARMV7-NEXT: vmovgt.f32 s3, s7
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmov.f32 s2, s0
+; ARMV7-NEXT: vcmp.f32 s5, #0
+; ARMV7-NEXT: vmovgt.f32 s2, s6
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmov.f32 s1, s0
+; ARMV7-NEXT: vcmp.f32 s4, #0
+; ARMV7-NEXT: vmovgt.f32 s1, s5
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmovgt.f32 s0, s4
+; ARMV7-NEXT: vmov r2, r3, d1
+; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr
+; ARMV7-NEXT: .p2align 2
+; ARMV7-NEXT: @ %bb.1:
+; ARMV7-NEXT: .LCPI21_0:
+; ARMV7-NEXT: .long 0x00000000 @ float 0
;
; ARMV8-LABEL: fmaxnumv432_zero_intrinsic:
; ARMV8: @ %bb.0:
@@ -834,13 +884,31 @@ define <4 x float> @fmaxnumv432_zero_intrinsic(<4 x float> %x) {
define <4 x float> @fmaxnumv432_minus_zero_intrinsic(<4 x float> %x) {
; ARMV7-LABEL: fmaxnumv432_minus_zero_intrinsic:
; ARMV7: @ %bb.0:
-; ARMV7-NEXT: vmov d19, r2, r3
-; ARMV7-NEXT: vmov.i32 q8, #0x80000000
-; ARMV7-NEXT: vmov d18, r0, r1
-; ARMV7-NEXT: vmax.f32 q8, q9, q8
-; ARMV7-NEXT: vmov r0, r1, d16
-; ARMV7-NEXT: vmov r2, r3, d17
+; ARMV7-NEXT: vldr s0, .LCPI22_0
+; ARMV7-NEXT: vmov d3, r2, r3
+; ARMV7-NEXT: vmov d2, r0, r1
+; ARMV7-NEXT: vcmp.f32 s7, s0
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmov.f32 s3, s0
+; ARMV7-NEXT: vcmp.f32 s6, s0
+; ARMV7-NEXT: vmovgt.f32 s3, s7
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmov.f32 s2, s0
+; ARMV7-NEXT: vcmp.f32 s5, s0
+; ARMV7-NEXT: vmovgt.f32 s2, s6
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmov.f32 s1, s0
+; ARMV7-NEXT: vcmp.f32 s4, s0
+; ARMV7-NEXT: vmovgt.f32 s1, s5
+; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
+; ARMV7-NEXT: vmovgt.f32 s0, s4
+; ARMV7-NEXT: vmov r2, r3, d1
+; ARMV7-NEXT: vmov r0, r1, d0
; ARMV7-NEXT: bx lr
+; ARMV7-NEXT: .p2align 2
+; ARMV7-NEXT: @ %bb.1:
+; ARMV7-NEXT: .LCPI22_0:
+; ARMV7-NEXT: .long 0x80000000 @ float -0
;
; ARMV8-LABEL: fmaxnumv432_minus_zero_intrinsic:
; ARMV8: @ %bb.0:
diff --git a/llvm/test/CodeGen/WebAssembly/f32.ll b/llvm/test/CodeGen/WebAssembly/f32.ll
index 33d9963afd92..3d7d312e0af9 100644
--- a/llvm/test/CodeGen/WebAssembly/f32.ll
+++ b/llvm/test/CodeGen/WebAssembly/f32.ll
@@ -217,10 +217,13 @@ define float @fminnum32_intrinsic(float %x, float %y) {
; CHECK-LABEL: fminnum32_intrinsic:
; CHECK: .functype fminnum32_intrinsic (f32, f32) -> (f32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push2=, 0
-; CHECK-NEXT: local.get $push1=, 1
-; CHECK-NEXT: f32.min $push0=, $pop2, $pop1
-; CHECK-NEXT: return $pop0
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: local.get $push4=, 1
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: local.get $push2=, 1
+; CHECK-NEXT: f32.lt $push0=, $pop3, $pop2
+; CHECK-NEXT: f32.select $push1=, $pop5, $pop4, $pop0
+; CHECK-NEXT: return $pop1
%a = call nnan float @llvm.minnum.f32(float %x, float %y)
ret float %a
}
@@ -267,10 +270,13 @@ define float @fmaxnum32_intrinsic(float %x, float %y) {
; CHECK-LABEL: fmaxnum32_intrinsic:
; CHECK: .functype fmaxnum32_intrinsic (f32, f32) -> (f32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push2=, 0
-; CHECK-NEXT: local.get $push1=, 1
-; CHECK-NEXT: f32.max $push0=, $pop2, $pop1
-; CHECK-NEXT: return $pop0
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: local.get $push4=, 1
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: local.get $push2=, 1
+; CHECK-NEXT: f32.gt $push0=, $pop3, $pop2
+; CHECK-NEXT: f32.select $push1=, $pop5, $pop4, $pop0
+; CHECK-NEXT: return $pop1
%a = call nnan float @llvm.maxnum.f32(float %x, float %y)
ret float %a
}
@@ -291,10 +297,13 @@ define float @fmaxnum32_zero_intrinsic(float %x) {
; CHECK-LABEL: fmaxnum32_zero_intrinsic:
; CHECK: .functype fmaxnum32_zero_intrinsic (f32) -> (f32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push5=, 0
; CHECK-NEXT: f32.const $push0=, 0x0p0
-; CHECK-NEXT: f32.max $push1=, $pop2, $pop0
-; CHECK-NEXT: return $pop1
+; CHECK-NEXT: local.get $push4=, 0
+; CHECK-NEXT: f32.const $push3=, 0x0p0
+; CHECK-NEXT: f32.gt $push1=, $pop4, $pop3
+; CHECK-NEXT: f32.select $push2=, $pop5, $pop0, $pop1
+; CHECK-NEXT: return $pop2
%a = call nnan float @llvm.maxnum.f32(float %x, float 0.0)
ret float %a
}
diff --git a/llvm/test/CodeGen/WebAssembly/f64.ll b/llvm/test/CodeGen/WebAssembly/f64.ll
index 59c532a46366..9c7d10de5509 100644
--- a/llvm/test/CodeGen/WebAssembly/f64.ll
+++ b/llvm/test/CodeGen/WebAssembly/f64.ll
@@ -217,10 +217,13 @@ define double @fminnum64_intrinsic(double %x, double %y) {
; CHECK-LABEL: fminnum64_intrinsic:
; CHECK: .functype fminnum64_intrinsic (f64, f64) -> (f64)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push2=, 0
-; CHECK-NEXT: local.get $push1=, 1
-; CHECK-NEXT: f64.min $push0=, $pop2, $pop1
-; CHECK-NEXT: return $pop0
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: local.get $push4=, 1
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: local.get $push2=, 1
+; CHECK-NEXT: f64.lt $push0=, $pop3, $pop2
+; CHECK-NEXT: f64.select $push1=, $pop5, $pop4, $pop0
+; CHECK-NEXT: return $pop1
%a = call nnan double @llvm.minnum.f64(double %x, double %y)
ret double %a
}
@@ -241,10 +244,13 @@ define double @fminnum64_zero_intrinsic(double %x) {
; CHECK-LABEL: fminnum64_zero_intrinsic:
; CHECK: .functype fminnum64_zero_intrinsic (f64) -> (f64)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push5=, 0
; CHECK-NEXT: f64.const $push0=, -0x0p0
-; CHECK-NEXT: f64.min $push1=, $pop2, $pop0
-; CHECK-NEXT: return $pop1
+; CHECK-NEXT: local.get $push4=, 0
+; CHECK-NEXT: f64.const $push3=, -0x0p0
+; CHECK-NEXT: f64.lt $push1=, $pop4, $pop3
+; CHECK-NEXT: f64.select $push2=, $pop5, $pop0, $pop1
+; CHECK-NEXT: return $pop2
%a = call nnan double @llvm.minnum.f64(double %x, double -0.0)
ret double %a
}
@@ -279,10 +285,13 @@ define double at fmaxnum64_intrinsic(double %x, double %y) {
; CHECK-LABEL: fmaxnum64_intrinsic:
; CHECK: .functype fmaxnum64_intrinsic (f64, f64) -> (f64)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push2=, 0
-; CHECK-NEXT: local.get $push1=, 1
-; CHECK-NEXT: f64.max $push0=, $pop2, $pop1
-; CHECK-NEXT: return $pop0
+; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: local.get $push4=, 1
+; CHECK-NEXT: local.get $push3=, 0
+; CHECK-NEXT: local.get $push2=, 1
+; CHECK-NEXT: f64.gt $push0=, $pop3, $pop2
+; CHECK-NEXT: f64.select $push1=, $pop5, $pop4, $pop0
+; CHECK-NEXT: return $pop1
%a = call nnan double @llvm.maxnum.f64(double %x, double %y)
ret double %a
}
@@ -303,10 +312,13 @@ define double @fmaxnum64_zero_intrinsic(double %x) {
; CHECK-LABEL: fmaxnum64_zero_intrinsic:
; CHECK: .functype fmaxnum64_zero_intrinsic (f64) -> (f64)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push5=, 0
; CHECK-NEXT: f64.const $push0=, 0x0p0
-; CHECK-NEXT: f64.max $push1=, $pop2, $pop0
-; CHECK-NEXT: return $pop1
+; CHECK-NEXT: local.get $push4=, 0
+; CHECK-NEXT: f64.const $push3=, 0x0p0
+; CHECK-NEXT: f64.gt $push1=, $pop4, $pop3
+; CHECK-NEXT: f64.select $push2=, $pop5, $pop0, $pop1
+; CHECK-NEXT: return $pop2
%a = call nnan double @llvm.maxnum.f64(double %x, double 0.0)
ret double %a
}
diff --git a/llvm/test/CodeGen/WebAssembly/simd-arith.ll b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
index ec55671a5ba0..7e0682be73b6 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-arith.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
@@ -13498,13 +13498,67 @@ define <4 x float> @minnum_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) {
; SIMD128-LABEL: minnum_intrinsic_v4f32:
; SIMD128: .functype minnum_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.min $push0=, $0, $1
-; SIMD128-NEXT: return $pop0
+; SIMD128-NEXT: f32x4.extract_lane $push27=, $0, 0
+; SIMD128-NEXT: local.tee $push26=, $3=, $pop27
+; SIMD128-NEXT: f32x4.extract_lane $push25=, $1, 0
+; SIMD128-NEXT: local.tee $push24=, $2=, $pop25
+; SIMD128-NEXT: f32.lt $push2=, $3, $2
+; SIMD128-NEXT: f32.select $push3=, $pop26, $pop24, $pop2
+; SIMD128-NEXT: f32x4.splat $push4=, $pop3
+; SIMD128-NEXT: f32x4.extract_lane $push23=, $0, 1
+; SIMD128-NEXT: local.tee $push22=, $3=, $pop23
+; SIMD128-NEXT: f32x4.extract_lane $push21=, $1, 1
+; SIMD128-NEXT: local.tee $push20=, $2=, $pop21
+; SIMD128-NEXT: f32.lt $push0=, $3, $2
+; SIMD128-NEXT: f32.select $push1=, $pop22, $pop20, $pop0
+; SIMD128-NEXT: f32x4.replace_lane $push5=, $pop4, 1, $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push19=, $0, 2
+; SIMD128-NEXT: local.tee $push18=, $3=, $pop19
+; SIMD128-NEXT: f32x4.extract_lane $push17=, $1, 2
+; SIMD128-NEXT: local.tee $push16=, $2=, $pop17
+; SIMD128-NEXT: f32.lt $push6=, $3, $2
+; SIMD128-NEXT: f32.select $push7=, $pop18, $pop16, $pop6
+; SIMD128-NEXT: f32x4.replace_lane $push8=, $pop5, 2, $pop7
+; SIMD128-NEXT: f32x4.extract_lane $push15=, $0, 3
+; SIMD128-NEXT: local.tee $push14=, $3=, $pop15
+; SIMD128-NEXT: f32x4.extract_lane $push13=, $1, 3
+; SIMD128-NEXT: local.tee $push12=, $2=, $pop13
+; SIMD128-NEXT: f32.lt $push9=, $3, $2
+; SIMD128-NEXT: f32.select $push10=, $pop14, $pop12, $pop9
+; SIMD128-NEXT: f32x4.replace_lane $push11=, $pop8, 3, $pop10
+; SIMD128-NEXT: return $pop11
;
; SIMD128-FAST-LABEL: minnum_intrinsic_v4f32:
; SIMD128-FAST: .functype minnum_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-FAST-NEXT: # %bb.0:
-; SIMD128-FAST-NEXT: f32x4.min $push0=, $0, $1
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push27=, $0, 0
+; SIMD128-FAST-NEXT: local.tee $push26=, $3=, $pop27
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push25=, $1, 0
+; SIMD128-FAST-NEXT: local.tee $push24=, $2=, $pop25
+; SIMD128-FAST-NEXT: f32.lt $push3=, $3, $2
+; SIMD128-FAST-NEXT: f32.select $push4=, $pop26, $pop24, $pop3
+; SIMD128-FAST-NEXT: f32x4.splat $push5=, $pop4
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push23=, $0, 1
+; SIMD128-FAST-NEXT: local.tee $push22=, $3=, $pop23
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push21=, $1, 1
+; SIMD128-FAST-NEXT: local.tee $push20=, $2=, $pop21
+; SIMD128-FAST-NEXT: f32.lt $push1=, $3, $2
+; SIMD128-FAST-NEXT: f32.select $push2=, $pop22, $pop20, $pop1
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push6=, $pop5, 1, $pop2
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push19=, $0, 2
+; SIMD128-FAST-NEXT: local.tee $push18=, $3=, $pop19
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push17=, $1, 2
+; SIMD128-FAST-NEXT: local.tee $push16=, $2=, $pop17
+; SIMD128-FAST-NEXT: f32.lt $push7=, $3, $2
+; SIMD128-FAST-NEXT: f32.select $push8=, $pop18, $pop16, $pop7
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push9=, $pop6, 2, $pop8
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push15=, $0, 3
+; SIMD128-FAST-NEXT: local.tee $push14=, $3=, $pop15
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push13=, $1, 3
+; SIMD128-FAST-NEXT: local.tee $push12=, $2=, $pop13
+; SIMD128-FAST-NEXT: f32.lt $push10=, $3, $2
+; SIMD128-FAST-NEXT: f32.select $push11=, $pop14, $pop12, $pop10
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push0=, $pop9, 3, $pop11
; SIMD128-FAST-NEXT: return $pop0
;
; NO-SIMD128-LABEL: minnum_intrinsic_v4f32:
@@ -13646,15 +13700,67 @@ define <4 x float> @fminnumv432_one_zero_intrinsic(<4 x float> %x) {
; SIMD128-LABEL: fminnumv432_one_zero_intrinsic:
; SIMD128: .functype fminnumv432_one_zero_intrinsic (v128) -> (v128)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: v128.const $push0=, -0x1p0, 0x0p0, -0x1p0, -0x1p0
-; SIMD128-NEXT: f32x4.min $push1=, $0, $pop0
-; SIMD128-NEXT: return $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push27=, $0, 0
+; SIMD128-NEXT: local.tee $push26=, $1=, $pop27
+; SIMD128-NEXT: f32.const $push3=, -0x1p0
+; SIMD128-NEXT: f32.const $push25=, -0x1p0
+; SIMD128-NEXT: f32.lt $push4=, $1, $pop25
+; SIMD128-NEXT: f32.select $push5=, $pop26, $pop3, $pop4
+; SIMD128-NEXT: f32x4.splat $push6=, $pop5
+; SIMD128-NEXT: f32x4.extract_lane $push24=, $0, 1
+; SIMD128-NEXT: local.tee $push23=, $1=, $pop24
+; SIMD128-NEXT: f32.const $push0=, 0x0p0
+; SIMD128-NEXT: f32.const $push22=, 0x0p0
+; SIMD128-NEXT: f32.lt $push1=, $1, $pop22
+; SIMD128-NEXT: f32.select $push2=, $pop23, $pop0, $pop1
+; SIMD128-NEXT: f32x4.replace_lane $push7=, $pop6, 1, $pop2
+; SIMD128-NEXT: f32x4.extract_lane $push21=, $0, 2
+; SIMD128-NEXT: local.tee $push20=, $1=, $pop21
+; SIMD128-NEXT: f32.const $push19=, -0x1p0
+; SIMD128-NEXT: f32.const $push18=, -0x1p0
+; SIMD128-NEXT: f32.lt $push8=, $1, $pop18
+; SIMD128-NEXT: f32.select $push9=, $pop20, $pop19, $pop8
+; SIMD128-NEXT: f32x4.replace_lane $push10=, $pop7, 2, $pop9
+; SIMD128-NEXT: f32x4.extract_lane $push17=, $0, 3
+; SIMD128-NEXT: local.tee $push16=, $1=, $pop17
+; SIMD128-NEXT: f32.const $push15=, -0x1p0
+; SIMD128-NEXT: f32.const $push14=, -0x1p0
+; SIMD128-NEXT: f32.lt $push11=, $1, $pop14
+; SIMD128-NEXT: f32.select $push12=, $pop16, $pop15, $pop11
+; SIMD128-NEXT: f32x4.replace_lane $push13=, $pop10, 3, $pop12
+; SIMD128-NEXT: return $pop13
;
; SIMD128-FAST-LABEL: fminnumv432_one_zero_intrinsic:
; SIMD128-FAST: .functype fminnumv432_one_zero_intrinsic (v128) -> (v128)
; SIMD128-FAST-NEXT: # %bb.0:
-; SIMD128-FAST-NEXT: v128.const $push1=, -0x1p0, 0x0p0, -0x1p0, -0x1p0
-; SIMD128-FAST-NEXT: f32x4.min $push0=, $0, $pop1
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push27=, $0, 0
+; SIMD128-FAST-NEXT: local.tee $push26=, $1=, $pop27
+; SIMD128-FAST-NEXT: f32.const $push4=, -0x1p0
+; SIMD128-FAST-NEXT: f32.const $push25=, -0x1p0
+; SIMD128-FAST-NEXT: f32.lt $push5=, $1, $pop25
+; SIMD128-FAST-NEXT: f32.select $push6=, $pop26, $pop4, $pop5
+; SIMD128-FAST-NEXT: f32x4.splat $push7=, $pop6
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push24=, $0, 1
+; SIMD128-FAST-NEXT: local.tee $push23=, $1=, $pop24
+; SIMD128-FAST-NEXT: f32.const $push1=, 0x0p0
+; SIMD128-FAST-NEXT: f32.const $push22=, 0x0p0
+; SIMD128-FAST-NEXT: f32.lt $push2=, $1, $pop22
+; SIMD128-FAST-NEXT: f32.select $push3=, $pop23, $pop1, $pop2
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push8=, $pop7, 1, $pop3
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push21=, $0, 2
+; SIMD128-FAST-NEXT: local.tee $push20=, $1=, $pop21
+; SIMD128-FAST-NEXT: f32.const $push19=, -0x1p0
+; SIMD128-FAST-NEXT: f32.const $push18=, -0x1p0
+; SIMD128-FAST-NEXT: f32.lt $push9=, $1, $pop18
+; SIMD128-FAST-NEXT: f32.select $push10=, $pop20, $pop19, $pop9
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push11=, $pop8, 2, $pop10
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push17=, $0, 3
+; SIMD128-FAST-NEXT: local.tee $push16=, $1=, $pop17
+; SIMD128-FAST-NEXT: f32.const $push15=, -0x1p0
+; SIMD128-FAST-NEXT: f32.const $push14=, -0x1p0
+; SIMD128-FAST-NEXT: f32.lt $push12=, $1, $pop14
+; SIMD128-FAST-NEXT: f32.select $push13=, $pop16, $pop15, $pop12
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push0=, $pop11, 3, $pop13
; SIMD128-FAST-NEXT: return $pop0
;
; NO-SIMD128-LABEL: fminnumv432_one_zero_intrinsic:
@@ -13750,13 +13856,67 @@ define <4 x float> @maxnum_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) {
; SIMD128-LABEL: maxnum_intrinsic_v4f32:
; SIMD128: .functype maxnum_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.max $push0=, $0, $1
-; SIMD128-NEXT: return $pop0
+; SIMD128-NEXT: f32x4.extract_lane $push27=, $0, 0
+; SIMD128-NEXT: local.tee $push26=, $3=, $pop27
+; SIMD128-NEXT: f32x4.extract_lane $push25=, $1, 0
+; SIMD128-NEXT: local.tee $push24=, $2=, $pop25
+; SIMD128-NEXT: f32.gt $push2=, $3, $2
+; SIMD128-NEXT: f32.select $push3=, $pop26, $pop24, $pop2
+; SIMD128-NEXT: f32x4.splat $push4=, $pop3
+; SIMD128-NEXT: f32x4.extract_lane $push23=, $0, 1
+; SIMD128-NEXT: local.tee $push22=, $3=, $pop23
+; SIMD128-NEXT: f32x4.extract_lane $push21=, $1, 1
+; SIMD128-NEXT: local.tee $push20=, $2=, $pop21
+; SIMD128-NEXT: f32.gt $push0=, $3, $2
+; SIMD128-NEXT: f32.select $push1=, $pop22, $pop20, $pop0
+; SIMD128-NEXT: f32x4.replace_lane $push5=, $pop4, 1, $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push19=, $0, 2
+; SIMD128-NEXT: local.tee $push18=, $3=, $pop19
+; SIMD128-NEXT: f32x4.extract_lane $push17=, $1, 2
+; SIMD128-NEXT: local.tee $push16=, $2=, $pop17
+; SIMD128-NEXT: f32.gt $push6=, $3, $2
+; SIMD128-NEXT: f32.select $push7=, $pop18, $pop16, $pop6
+; SIMD128-NEXT: f32x4.replace_lane $push8=, $pop5, 2, $pop7
+; SIMD128-NEXT: f32x4.extract_lane $push15=, $0, 3
+; SIMD128-NEXT: local.tee $push14=, $3=, $pop15
+; SIMD128-NEXT: f32x4.extract_lane $push13=, $1, 3
+; SIMD128-NEXT: local.tee $push12=, $2=, $pop13
+; SIMD128-NEXT: f32.gt $push9=, $3, $2
+; SIMD128-NEXT: f32.select $push10=, $pop14, $pop12, $pop9
+; SIMD128-NEXT: f32x4.replace_lane $push11=, $pop8, 3, $pop10
+; SIMD128-NEXT: return $pop11
;
; SIMD128-FAST-LABEL: maxnum_intrinsic_v4f32:
; SIMD128-FAST: .functype maxnum_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-FAST-NEXT: # %bb.0:
-; SIMD128-FAST-NEXT: f32x4.max $push0=, $0, $1
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push27=, $0, 0
+; SIMD128-FAST-NEXT: local.tee $push26=, $3=, $pop27
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push25=, $1, 0
+; SIMD128-FAST-NEXT: local.tee $push24=, $2=, $pop25
+; SIMD128-FAST-NEXT: f32.gt $push3=, $3, $2
+; SIMD128-FAST-NEXT: f32.select $push4=, $pop26, $pop24, $pop3
+; SIMD128-FAST-NEXT: f32x4.splat $push5=, $pop4
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push23=, $0, 1
+; SIMD128-FAST-NEXT: local.tee $push22=, $3=, $pop23
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push21=, $1, 1
+; SIMD128-FAST-NEXT: local.tee $push20=, $2=, $pop21
+; SIMD128-FAST-NEXT: f32.gt $push1=, $3, $2
+; SIMD128-FAST-NEXT: f32.select $push2=, $pop22, $pop20, $pop1
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push6=, $pop5, 1, $pop2
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push19=, $0, 2
+; SIMD128-FAST-NEXT: local.tee $push18=, $3=, $pop19
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push17=, $1, 2
+; SIMD128-FAST-NEXT: local.tee $push16=, $2=, $pop17
+; SIMD128-FAST-NEXT: f32.gt $push7=, $3, $2
+; SIMD128-FAST-NEXT: f32.select $push8=, $pop18, $pop16, $pop7
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push9=, $pop6, 2, $pop8
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push15=, $0, 3
+; SIMD128-FAST-NEXT: local.tee $push14=, $3=, $pop15
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push13=, $1, 3
+; SIMD128-FAST-NEXT: local.tee $push12=, $2=, $pop13
+; SIMD128-FAST-NEXT: f32.gt $push10=, $3, $2
+; SIMD128-FAST-NEXT: f32.select $push11=, $pop14, $pop12, $pop10
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push0=, $pop9, 3, $pop11
; SIMD128-FAST-NEXT: return $pop0
;
; NO-SIMD128-LABEL: maxnum_intrinsic_v4f32:
@@ -13842,15 +14002,67 @@ define <4 x float> @maxnum_one_zero_intrinsic_v4f32(<4 x float> %x, <4 x float>
; SIMD128-LABEL: maxnum_one_zero_intrinsic_v4f32:
; SIMD128: .functype maxnum_one_zero_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: v128.const $push0=, -0x1p0, 0x0p0, -0x1p0, -0x1p0
-; SIMD128-NEXT: f32x4.max $push1=, $0, $pop0
-; SIMD128-NEXT: return $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push27=, $0, 0
+; SIMD128-NEXT: local.tee $push26=, $2=, $pop27
+; SIMD128-NEXT: f32.const $push3=, -0x1p0
+; SIMD128-NEXT: f32.const $push25=, -0x1p0
+; SIMD128-NEXT: f32.gt $push4=, $2, $pop25
+; SIMD128-NEXT: f32.select $push5=, $pop26, $pop3, $pop4
+; SIMD128-NEXT: f32x4.splat $push6=, $pop5
+; SIMD128-NEXT: f32x4.extract_lane $push24=, $0, 1
+; SIMD128-NEXT: local.tee $push23=, $2=, $pop24
+; SIMD128-NEXT: f32.const $push0=, 0x0p0
+; SIMD128-NEXT: f32.const $push22=, 0x0p0
+; SIMD128-NEXT: f32.gt $push1=, $2, $pop22
+; SIMD128-NEXT: f32.select $push2=, $pop23, $pop0, $pop1
+; SIMD128-NEXT: f32x4.replace_lane $push7=, $pop6, 1, $pop2
+; SIMD128-NEXT: f32x4.extract_lane $push21=, $0, 2
+; SIMD128-NEXT: local.tee $push20=, $2=, $pop21
+; SIMD128-NEXT: f32.const $push19=, -0x1p0
+; SIMD128-NEXT: f32.const $push18=, -0x1p0
+; SIMD128-NEXT: f32.gt $push8=, $2, $pop18
+; SIMD128-NEXT: f32.select $push9=, $pop20, $pop19, $pop8
+; SIMD128-NEXT: f32x4.replace_lane $push10=, $pop7, 2, $pop9
+; SIMD128-NEXT: f32x4.extract_lane $push17=, $0, 3
+; SIMD128-NEXT: local.tee $push16=, $2=, $pop17
+; SIMD128-NEXT: f32.const $push15=, -0x1p0
+; SIMD128-NEXT: f32.const $push14=, -0x1p0
+; SIMD128-NEXT: f32.gt $push11=, $2, $pop14
+; SIMD128-NEXT: f32.select $push12=, $pop16, $pop15, $pop11
+; SIMD128-NEXT: f32x4.replace_lane $push13=, $pop10, 3, $pop12
+; SIMD128-NEXT: return $pop13
;
; SIMD128-FAST-LABEL: maxnum_one_zero_intrinsic_v4f32:
; SIMD128-FAST: .functype maxnum_one_zero_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-FAST-NEXT: # %bb.0:
-; SIMD128-FAST-NEXT: v128.const $push1=, -0x1p0, 0x0p0, -0x1p0, -0x1p0
-; SIMD128-FAST-NEXT: f32x4.max $push0=, $0, $pop1
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push27=, $0, 0
+; SIMD128-FAST-NEXT: local.tee $push26=, $2=, $pop27
+; SIMD128-FAST-NEXT: f32.const $push4=, -0x1p0
+; SIMD128-FAST-NEXT: f32.const $push25=, -0x1p0
+; SIMD128-FAST-NEXT: f32.gt $push5=, $2, $pop25
+; SIMD128-FAST-NEXT: f32.select $push6=, $pop26, $pop4, $pop5
+; SIMD128-FAST-NEXT: f32x4.splat $push7=, $pop6
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push24=, $0, 1
+; SIMD128-FAST-NEXT: local.tee $push23=, $2=, $pop24
+; SIMD128-FAST-NEXT: f32.const $push1=, 0x0p0
+; SIMD128-FAST-NEXT: f32.const $push22=, 0x0p0
+; SIMD128-FAST-NEXT: f32.gt $push2=, $2, $pop22
+; SIMD128-FAST-NEXT: f32.select $push3=, $pop23, $pop1, $pop2
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push8=, $pop7, 1, $pop3
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push21=, $0, 2
+; SIMD128-FAST-NEXT: local.tee $push20=, $2=, $pop21
+; SIMD128-FAST-NEXT: f32.const $push19=, -0x1p0
+; SIMD128-FAST-NEXT: f32.const $push18=, -0x1p0
+; SIMD128-FAST-NEXT: f32.gt $push9=, $2, $pop18
+; SIMD128-FAST-NEXT: f32.select $push10=, $pop20, $pop19, $pop9
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push11=, $pop8, 2, $pop10
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push17=, $0, 3
+; SIMD128-FAST-NEXT: local.tee $push16=, $2=, $pop17
+; SIMD128-FAST-NEXT: f32.const $push15=, -0x1p0
+; SIMD128-FAST-NEXT: f32.const $push14=, -0x1p0
+; SIMD128-FAST-NEXT: f32.gt $push12=, $2, $pop14
+; SIMD128-FAST-NEXT: f32.select $push13=, $pop16, $pop15, $pop12
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push0=, $pop11, 3, $pop13
; SIMD128-FAST-NEXT: return $pop0
;
; NO-SIMD128-LABEL: maxnum_one_zero_intrinsic_v4f32:
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