[PATCH] D143475: [AArch64] Fix creation of invalid instructions with XZR register

Tue Feb 7 00:56:28 PST 2023

dmgreen created this revision.
dmgreen added reviewers: jaykang10, efriedma, red1bluelost, bipmis.
Herald added subscribers: hiraditya, kristof.beyls.
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dmgreen requested review of this revision.
Herald added a project: LLVM.

A combination of GlobalISel and MachineCombiner can end up creating `SUB xrz, (MOVI -2105098)` instructions which have not been constant folded. The  AArch64MIPeepholeOpt pass will then attempt to create `ADD xzr, 513, lsl 12`, which is not a valid instruction. This adds a bail out of the transform if the register is xzr/wzr.

https://reviews.llvm.org/D143475

Files:
  llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
  llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir

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