[llvm] 341b1df - [AArch64][SVE] Fix crash for DestructiveBinaryCommWithRev zero merging
via llvm-commits
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Mon Feb 6 19:13:59 PST 2023
Author: zhongyunde
Date: 2023-02-07T11:10:27+08:00
New Revision: 341b1df5bc7ed0baa258592a35a7458a310e43a9
URL: https://github.com/llvm/llvm-project/commit/341b1df5bc7ed0baa258592a35a7458a310e43a9
DIFF: https://github.com/llvm/llvm-project/commit/341b1df5bc7ed0baa258592a35a7458a310e43a9.diff
LOG: [AArch64][SVE] Fix crash for DestructiveBinaryCommWithRev zero merging
Address more Destructive type according the review on D141471
* DestructiveUnaryPassthru and DestructiveBinaryImm always return true, don't need fix
* DestructiveTernaryCommWithRev may also return false, but now don't define FalseLanesZero in the backend codegen
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D142978
Added:
llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
Modified:
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 11f1d4a8a4b7..71c6ae1e34e2 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -589,7 +589,8 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
// If we cannot prefix the requested instruction we'll instead emit a
// prefixed_zeroing_mov for DestructiveBinary.
assert((DOPRegIsUnique || DType == AArch64::DestructiveBinary ||
- DType == AArch64::DestructiveBinaryComm) &&
+ DType == AArch64::DestructiveBinaryComm ||
+ DType == AArch64::DestructiveBinaryCommWithRev) &&
"The destructive operand should be unique");
assert(ElementSize != AArch64::ElementSizeNone &&
"This instruction is unpredicated");
@@ -607,7 +608,8 @@ bool AArch64ExpandPseudo::expand_DestructiveOp(
// unique. Zeros the lanes in z0 that aren't active in p0 with sequence
// movprfx z0.b, p0/z, z0.b; lsl z0.b, p0/m, z0.b, #0;
if ((DType == AArch64::DestructiveBinary ||
- DType == AArch64::DestructiveBinaryComm) &&
+ DType == AArch64::DestructiveBinaryComm ||
+ DType == AArch64::DestructiveBinaryCommWithRev) &&
!DOPRegIsUnique) {
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LSLZero))
.addReg(DstReg, RegState::Define)
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
new file mode 100644
index 000000000000..8e6007dde5ef
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
@@ -0,0 +1,41 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s
+
+# Should create an additional LSL to zero the lanes as the DstReg is not unique
+
+--- |
+ define <vscale x 4 x float> @fsub_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a){
+ %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+ %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg,
+ <vscale x 4 x float> %a_z,
+ <vscale x 4 x float> %a_z)
+ ret <vscale x 4 x float> %out
+ }
+
+ declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+...
+---
+name: fsub_s_zero
+alignment: 4
+tracksRegLiveness: true
+tracksDebugUserValues: true
+registers: []
+liveins:
+ - { reg: '$p0', virtual-reg: '' }
+ - { reg: '$z0', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $p0, $z0
+
+ ; CHECK-LABEL: name: fsub_s_zero
+ ; CHECK: liveins: $p0, $z0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $z0_hi, implicit $p0, implicit $z0 {
+ ; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0
+ ; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0
+ ; CHECK-NEXT: $z0 = FSUBR_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0
+ ; CHECK-NEXT: }
+ ; CHECK-NEXT: RET undef $lr, implicit $z0
+ renamable $z0 = nnan ninf nsz arcp contract afn reassoc FSUB_ZPZZ_ZERO_S renamable $p0, killed renamable $z0, renamable $z0
+ RET_ReallyLR implicit $z0
+...
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