[PATCH] D142348: [RISCV][Docs] Document code generation for vector extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/docs/RISCV/RISCVVectorExtension.rst:185
+
+One downside of this design is that doesn’t allow vectors of i128 (this is, ELEN=128). In that case vscale would have to be 1/2 under :math:`\text{LMUL}=1`. This type (and its fp counterpart float128) are not that common and in case of extreme necessity types for :math:`\text{LMUL}=2` could be used instead.
+
----------------
luke wrote:
> craig.topper wrote:
> > This mapping also prevents the value of vscale from being examined if ELEN and VLEN are both 32.
> I'm not sure if I understand, could you clarified by what you mean by examined? Is it related to https://reviews.llvm.org/D128286
We can't use llvm.vscale or ISD:VSCALE if ELEN is 32. See this code in RISCVISelLowering.cpp. Specifically the fatal_error.

```
  case ISD::VSCALE: {
    MVT VT = Op.getSimpleValueType();
    SDLoc DL(Op);
    SDValue VLENB = DAG.getNode(RISCVISD::READ_VLENB, DL, VT);
    // We define our scalable vector types for lmul=1 to use a 64 bit known
    // minimum size. e.g. <vscale x 2 x i32>. VLENB is in bytes so we calculate
    // vscale as VLENB / 8.
    static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
    if (Subtarget.getRealMinVLen() < RISCV::RVVBitsPerBlock)
      report_fatal_error("Support for VLEN==32 is incomplete.");
```


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  https://reviews.llvm.org/D142348/new/

https://reviews.llvm.org/D142348