[llvm] 254e2ad - [AArch64][GlobalISel] Widen G_ADD/G_MUL/G_OR/... element types if size < 8b
Vladislav Dzhidzhoev via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 6 14:34:17 PST 2023
Author: Vladislav Dzhidzhoev
Date: 2023-02-06T23:33:58+01:00
New Revision: 254e2ad84407fce81f3b0c07e75f23671b8cb56a
URL: https://github.com/llvm/llvm-project/commit/254e2ad84407fce81f3b0c07e75f23671b8cb56a
DIFF: https://github.com/llvm/llvm-project/commit/254e2ad84407fce81f3b0c07e75f23671b8cb56a.diff
LOG: [AArch64][GlobalISel] Widen G_ADD/G_MUL/G_OR/... element types if size < 8b
Widen element types of vector arguments of G_ADD, G_SUB, G_MUL, G_AND,
G_OR, G_XOR to the minumum supported size, in order to support vectors
of narrow types.
Differential Revision: https://reviews.llvm.org/D143100
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 7e5fd1a5f6bdf..38a14d0579759 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -128,6 +128,21 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampScalar(0, s32, s64)
.clampNumElements(0, v2s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
+ .minScalarOrEltIf(
+ [=](const LegalityQuery &Query) {
+ return Query.Types[0].getNumElements() <= 2;
+ },
+ 0, s32)
+ .minScalarOrEltIf(
+ [=](const LegalityQuery &Query) {
+ return Query.Types[0].getNumElements() <= 4;
+ },
+ 0, s16)
+ .minScalarOrEltIf(
+ [=](const LegalityQuery &Query) {
+ return Query.Types[0].getNumElements() <= 16;
+ },
+ 0, s8)
.moreElementsToNextPow2(0);
getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
index d27aa46225e56..20deef9e836bb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
@@ -282,4 +282,159 @@ body: |
%2:_(<8 x s8>) = G_ADD %0, %1
$d0 = COPY %2(<8 x s8>)
RET_ReallyLR implicit $d0
+
+...
+---
+name: add_v2s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: add_v2s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s32>) = G_ADD [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[ADD]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<2 x s32>) = COPY $d0
+ %1:_(<2 x s32>) = COPY $d1
+ %2:_(<2 x s32>) = COPY $d2
+ %3:_(<2 x s32>) = COPY $d3
+ %4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
+ %5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3
+ %6:_(<2 x s1>) = G_ADD %4, %5
+ %7:_(<2 x s32>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<2 x s32>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: add_v3s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $b0, $b1, $b2
+
+ ; CHECK-LABEL: name: add_v3s1
+ ; CHECK: liveins: $b0, $b1, $b2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
+ ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
+ ; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s16>) = G_ADD [[BUILD_VECTOR]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[ADD]](<4 x s16>)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
+ ; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
+ ; CHECK-NEXT: RET_ReallyLR implicit $b0
+ %1:_(s8) = COPY $b0
+ %2:_(s8) = COPY $b1
+ %3:_(s8) = COPY $b2
+ %4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)
+ %0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)
+ %5:_(<3 x s1>) = G_ADD %0, %0
+ %7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)
+ %8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)
+ $b0 = COPY %8:_(s8)
+ RET_ReallyLR implicit $b0
+...
+---
+name: add_v4s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: add_v4s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s16>) = G_ADD [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[ADD]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>) = COPY $d2
+ %3:_(<4 x s16>) = COPY $d3
+ %4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
+ %5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3
+ %6:_(<4 x s1>) = G_ADD %4, %5
+ %7:_(<4 x s16>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<4 x s16>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: add_v8s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: add_v8s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s8>) = G_ADD [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[ADD]](<8 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s8>) = COPY $d2
+ %3:_(<8 x s8>) = COPY $d3
+ %4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
+ %5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3
+ %6:_(<8 x s1>) = G_ADD %4, %5
+ %7:_(<8 x s8>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<8 x s8>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: add_v16s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $q0, $q1, $q2, $q3
+
+ ; CHECK-LABEL: name: add_v16s1
+ ; CHECK: liveins: $q0, $q1, $q2, $q3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $q0 = COPY [[ADD]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %0:_(<16 x s8>) = COPY $q0
+ %1:_(<16 x s8>) = COPY $q1
+ %2:_(<16 x s8>) = COPY $q2
+ %3:_(<16 x s8>) = COPY $q3
+ %4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
+ %5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3
+ %6:_(<16 x s1>) = G_ADD %4, %5
+ %7:_(<16 x s8>) = G_ANYEXT %6
+ $q0 = COPY %7:_(<16 x s8>)
+ RET_ReallyLR implicit $q0
...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
index 68a388967899d..f902de35e4eb4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
@@ -158,3 +158,159 @@ body: |
%and:_(s318) = G_AND %a, %b
G_STORE %and(s318), %ptr(p0) :: (store (s318))
RET_ReallyLR implicit $x0
+
+...
+---
+name: and_v2s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: and_v2s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[AND]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<2 x s32>) = COPY $d0
+ %1:_(<2 x s32>) = COPY $d1
+ %2:_(<2 x s32>) = COPY $d2
+ %3:_(<2 x s32>) = COPY $d3
+ %4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
+ %5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3
+ %6:_(<2 x s1>) = G_AND %4, %5
+ %7:_(<2 x s32>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<2 x s32>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: and_v3s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $b0, $b1, $b2
+
+ ; CHECK-LABEL: name: and_v3s1
+ ; CHECK: liveins: $b0, $b1, $b2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
+ ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
+ ; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[AND]](<4 x s16>)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
+ ; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
+ ; CHECK-NEXT: RET_ReallyLR implicit $b0
+ %1:_(s8) = COPY $b0
+ %2:_(s8) = COPY $b1
+ %3:_(s8) = COPY $b2
+ %4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)
+ %0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)
+ %5:_(<3 x s1>) = G_AND %0, %0
+ %7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)
+ %8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)
+ $b0 = COPY %8:_(s8)
+ RET_ReallyLR implicit $b0
+...
+---
+name: and_v4s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: and_v4s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[AND]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>) = COPY $d2
+ %3:_(<4 x s16>) = COPY $d3
+ %4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
+ %5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3
+ %6:_(<4 x s1>) = G_AND %4, %5
+ %7:_(<4 x s16>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<4 x s16>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: and_v8s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: and_v8s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s8>) = G_AND [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[AND]](<8 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s8>) = COPY $d2
+ %3:_(<8 x s8>) = COPY $d3
+ %4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
+ %5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3
+ %6:_(<8 x s1>) = G_AND %4, %5
+ %7:_(<8 x s8>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<8 x s8>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: and_v16s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $q0, $q1, $q2, $q3
+
+ ; CHECK-LABEL: name: and_v16s1
+ ; CHECK: liveins: $q0, $q1, $q2, $q3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $q0 = COPY [[AND]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %0:_(<16 x s8>) = COPY $q0
+ %1:_(<16 x s8>) = COPY $q1
+ %2:_(<16 x s8>) = COPY $q2
+ %3:_(<16 x s8>) = COPY $q3
+ %4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
+ %5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3
+ %6:_(<16 x s1>) = G_AND %4, %5
+ %7:_(<16 x s8>) = G_ANYEXT %6
+ $q0 = COPY %7:_(<16 x s8>)
+ RET_ReallyLR implicit $q0
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
index 537bec3edd7d2..d593d701be60e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
@@ -457,3 +457,157 @@ body: |
RET_ReallyLR implicit $q0
...
+---
+name: mul_v2s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: mul_v2s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<2 x s32>) = G_MUL [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[MUL]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<2 x s32>) = COPY $d0
+ %1:_(<2 x s32>) = COPY $d1
+ %2:_(<2 x s32>) = COPY $d2
+ %3:_(<2 x s32>) = COPY $d3
+ %4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
+ %5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3
+ %6:_(<2 x s1>) = G_MUL %4, %5
+ %7:_(<2 x s32>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<2 x s32>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: mul_v3s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $b0, $b1, $b2
+
+ ; CHECK-LABEL: name: mul_v3s1
+ ; CHECK: liveins: $b0, $b1, $b2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
+ ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
+ ; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s16>) = G_MUL [[BUILD_VECTOR]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[MUL]](<4 x s16>)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
+ ; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
+ ; CHECK-NEXT: RET_ReallyLR implicit $b0
+ %1:_(s8) = COPY $b0
+ %2:_(s8) = COPY $b1
+ %3:_(s8) = COPY $b2
+ %4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)
+ %0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)
+ %5:_(<3 x s1>) = G_MUL %0, %0
+ %7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)
+ %8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)
+ $b0 = COPY %8:_(s8)
+ RET_ReallyLR implicit $b0
+...
+---
+name: mul_v4s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: mul_v4s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s16>) = G_MUL [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[MUL]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>) = COPY $d2
+ %3:_(<4 x s16>) = COPY $d3
+ %4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
+ %5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3
+ %6:_(<4 x s1>) = G_MUL %4, %5
+ %7:_(<4 x s16>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<4 x s16>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: mul_v8s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: mul_v8s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<8 x s8>) = G_MUL [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[MUL]](<8 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s8>) = COPY $d2
+ %3:_(<8 x s8>) = COPY $d3
+ %4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
+ %5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3
+ %6:_(<8 x s1>) = G_MUL %4, %5
+ %7:_(<8 x s8>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<8 x s8>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: mul_v16s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $q0, $q1, $q2, $q3
+
+ ; CHECK-LABEL: name: mul_v16s1
+ ; CHECK: liveins: $q0, $q1, $q2, $q3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $q0 = COPY [[MUL]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %0:_(<16 x s8>) = COPY $q0
+ %1:_(<16 x s8>) = COPY $q1
+ %2:_(<16 x s8>) = COPY $q2
+ %3:_(<16 x s8>) = COPY $q3
+ %4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
+ %5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3
+ %6:_(<16 x s1>) = G_MUL %4, %5
+ %7:_(<16 x s8>) = G_ANYEXT %6
+ $q0 = COPY %7:_(<16 x s8>)
+ RET_ReallyLR implicit $q0
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
index f1ca75348db28..a2782af273034 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
@@ -98,3 +98,159 @@ body: |
%or:_(s318) = G_OR %a, %b
G_STORE %or(s318), %ptr(p0) :: (store (s318))
RET_ReallyLR implicit $x0
+
+...
+---
+name: or_v2s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: or_v2s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[OR]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<2 x s32>) = COPY $d0
+ %1:_(<2 x s32>) = COPY $d1
+ %2:_(<2 x s32>) = COPY $d2
+ %3:_(<2 x s32>) = COPY $d3
+ %4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
+ %5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3
+ %6:_(<2 x s1>) = G_OR %4, %5
+ %7:_(<2 x s32>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<2 x s32>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: or_v3s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $b0, $b1, $b2
+
+ ; CHECK-LABEL: name: or_v3s1
+ ; CHECK: liveins: $b0, $b1, $b2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
+ ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
+ ; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[BUILD_VECTOR]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR]](<4 x s16>)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
+ ; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
+ ; CHECK-NEXT: RET_ReallyLR implicit $b0
+ %1:_(s8) = COPY $b0
+ %2:_(s8) = COPY $b1
+ %3:_(s8) = COPY $b2
+ %4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)
+ %0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)
+ %5:_(<3 x s1>) = G_OR %0, %0
+ %7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)
+ %8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)
+ $b0 = COPY %8:_(s8)
+ RET_ReallyLR implicit $b0
+...
+---
+name: or_v4s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: or_v4s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[OR]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>) = COPY $d2
+ %3:_(<4 x s16>) = COPY $d3
+ %4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
+ %5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3
+ %6:_(<4 x s1>) = G_OR %4, %5
+ %7:_(<4 x s16>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<4 x s16>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: or_v8s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: or_v8s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s8>) = G_OR [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[OR]](<8 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s8>) = COPY $d2
+ %3:_(<8 x s8>) = COPY $d3
+ %4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
+ %5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3
+ %6:_(<8 x s1>) = G_OR %4, %5
+ %7:_(<8 x s8>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<8 x s8>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: or_v16s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $q0, $q1, $q2, $q3
+
+ ; CHECK-LABEL: name: or_v16s1
+ ; CHECK: liveins: $q0, $q1, $q2, $q3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $q0 = COPY [[OR]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %0:_(<16 x s8>) = COPY $q0
+ %1:_(<16 x s8>) = COPY $q1
+ %2:_(<16 x s8>) = COPY $q2
+ %3:_(<16 x s8>) = COPY $q3
+ %4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
+ %5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3
+ %6:_(<16 x s1>) = G_OR %4, %5
+ %7:_(<16 x s8>) = G_ANYEXT %6
+ $q0 = COPY %7:_(<16 x s8>)
+ RET_ReallyLR implicit $q0
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
index 5d556a69537b8..31b87a04a6dc1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
@@ -304,12 +304,25 @@ body: |
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C2]](s64)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s1>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s1>), [[DEF]], shufflemask(0, 0, 0, 0)
- ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
- ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s1>) = G_BUILD_VECTOR [[C3]](s1), [[C3]](s1), [[C3]](s1), [[C3]](s1)
- ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s1>) = G_XOR [[SHUF]], [[BUILD_VECTOR1]]
- ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s1>) = G_AND %vec_cond0, [[SHUF]]
- ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s1>) = G_AND %vec_cond1, [[XOR]]
- ; CHECK-NEXT: %select:_(<4 x s1>) = G_OR [[AND]], [[AND1]]
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[C3]](s8)
+ ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s1>) = G_BUILD_VECTOR [[TRUNC1]](s1), [[TRUNC1]](s1), [[TRUNC1]](s1), [[TRUNC1]](s1)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[SHUF]](<4 x s1>)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[BUILD_VECTOR1]](<4 x s1>)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[ANYEXT]], [[ANYEXT1]]
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[XOR]](<4 x s16>)
+ ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT %vec_cond0(<4 x s1>)
+ ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[SHUF]](<4 x s1>)
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[ANYEXT3]], [[ANYEXT4]]
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[AND]](<4 x s16>)
+ ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT %vec_cond1(<4 x s1>)
+ ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC2]](<4 x s1>)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s16>) = G_AND [[ANYEXT5]], [[ANYEXT6]]
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[AND1]](<4 x s16>)
+ ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC3]](<4 x s1>)
+ ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[TRUNC4]](<4 x s1>)
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[ANYEXT7]], [[ANYEXT8]]
+ ; CHECK-NEXT: %select:_(<4 x s1>) = G_TRUNC [[OR]](<4 x s16>)
; CHECK-NEXT: %zext_select:_(<4 x s32>) = G_ZEXT %select(<4 x s1>)
; CHECK-NEXT: $q0 = COPY %zext_select(<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
index 159470c47664d..54183f9abacad 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
@@ -80,3 +80,157 @@ body: |
$x0 = COPY %5(s64)
...
+---
+name: sub_v2s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: sub_v2s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
+ ; CHECK-NEXT: [[sub:%[0-9]+]]:_(<2 x s32>) = G_SUB [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[sub]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<2 x s32>) = COPY $d0
+ %1:_(<2 x s32>) = COPY $d1
+ %2:_(<2 x s32>) = COPY $d2
+ %3:_(<2 x s32>) = COPY $d3
+ %4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
+ %5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3
+ %6:_(<2 x s1>) = G_SUB %4, %5
+ %7:_(<2 x s32>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<2 x s32>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: sub_v3s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $b0, $b1, $b2
+
+ ; CHECK-LABEL: name: sub_v3s1
+ ; CHECK: liveins: $b0, $b1, $b2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
+ ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
+ ; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s16>) = G_SUB [[BUILD_VECTOR]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[SUB]](<4 x s16>)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
+ ; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
+ ; CHECK-NEXT: RET_ReallyLR implicit $b0
+ %1:_(s8) = COPY $b0
+ %2:_(s8) = COPY $b1
+ %3:_(s8) = COPY $b2
+ %4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)
+ %0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)
+ %5:_(<3 x s1>) = G_SUB %0, %0
+ %7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)
+ %8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)
+ $b0 = COPY %8:_(s8)
+ RET_ReallyLR implicit $b0
+...
+---
+name: sub_v4s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: sub_v4s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
+ ; CHECK-NEXT: [[sub:%[0-9]+]]:_(<4 x s16>) = G_SUB [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[sub]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>) = COPY $d2
+ %3:_(<4 x s16>) = COPY $d3
+ %4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
+ %5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3
+ %6:_(<4 x s1>) = G_SUB %4, %5
+ %7:_(<4 x s16>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<4 x s16>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: sub_v8s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: sub_v8s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[sub:%[0-9]+]]:_(<8 x s8>) = G_SUB [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[sub]](<8 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s8>) = COPY $d2
+ %3:_(<8 x s8>) = COPY $d3
+ %4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
+ %5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3
+ %6:_(<8 x s1>) = G_SUB %4, %5
+ %7:_(<8 x s8>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<8 x s8>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: sub_v16s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $q0, $q1, $q2, $q3
+
+ ; CHECK-LABEL: name: sub_v16s1
+ ; CHECK: liveins: $q0, $q1, $q2, $q3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[sub:%[0-9]+]]:_(<16 x s8>) = G_SUB [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $q0 = COPY [[sub]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %0:_(<16 x s8>) = COPY $q0
+ %1:_(<16 x s8>) = COPY $q1
+ %2:_(<16 x s8>) = COPY $q2
+ %3:_(<16 x s8>) = COPY $q3
+ %4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
+ %5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3
+ %6:_(<16 x s1>) = G_SUB %4, %5
+ %7:_(<16 x s8>) = G_ANYEXT %6
+ $q0 = COPY %7:_(<16 x s8>)
+ RET_ReallyLR implicit $q0
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
index 1a4c2b9c8e53a..f4cdd90d2c930 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
@@ -145,3 +145,159 @@ body: |
%xor:_(s158) = G_XOR %a, %b
G_STORE %xor(s158), %ptr(p0) :: (store (s158))
RET_ReallyLR implicit $x0
+
+...
+---
+name: xor_v2s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: xor_v2s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s32>) = G_XOR [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[XOR]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<2 x s32>) = COPY $d0
+ %1:_(<2 x s32>) = COPY $d1
+ %2:_(<2 x s32>) = COPY $d2
+ %3:_(<2 x s32>) = COPY $d3
+ %4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
+ %5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3
+ %6:_(<2 x s1>) = G_XOR %4, %5
+ %7:_(<2 x s32>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<2 x s32>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: xor_v3s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $b0, $b1, $b2
+
+ ; CHECK-LABEL: name: xor_v3s1
+ ; CHECK: liveins: $b0, $b1, $b2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
+ ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
+ ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
+ ; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[BUILD_VECTOR]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[XOR]](<4 x s16>)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
+ ; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
+ ; CHECK-NEXT: RET_ReallyLR implicit $b0
+ %1:_(s8) = COPY $b0
+ %2:_(s8) = COPY $b1
+ %3:_(s8) = COPY $b2
+ %4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)
+ %0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)
+ %5:_(<3 x s1>) = G_XOR %0, %0
+ %7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)
+ %8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)
+ $b0 = COPY %8:_(s8)
+ RET_ReallyLR implicit $b0
+...
+---
+name: xor_v4s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: xor_v4s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[XOR]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>) = COPY $d2
+ %3:_(<4 x s16>) = COPY $d3
+ %4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
+ %5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3
+ %6:_(<4 x s1>) = G_XOR %4, %5
+ %7:_(<4 x s16>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<4 x s16>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: xor_v8s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $d0, $d1, $d2, $d3
+
+ ; CHECK-LABEL: name: xor_v8s1
+ ; CHECK: liveins: $d0, $d1, $d2, $d3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s8>) = G_XOR [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $d0 = COPY [[XOR]](<8 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ %0:_(<8 x s8>) = COPY $d0
+ %1:_(<8 x s8>) = COPY $d1
+ %2:_(<8 x s8>) = COPY $d2
+ %3:_(<8 x s8>) = COPY $d3
+ %4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
+ %5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3
+ %6:_(<8 x s1>) = G_XOR %4, %5
+ %7:_(<8 x s8>) = G_ANYEXT %6
+ $d0 = COPY %7:_(<8 x s8>)
+ RET_ReallyLR implicit $d0
+...
+---
+name: xor_v16s1
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $q0, $q1, $q2, $q3
+
+ ; CHECK-LABEL: name: xor_v16s1
+ ; CHECK: liveins: $q0, $q1, $q2, $q3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<16 x s8>) = G_XOR [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: $q0 = COPY [[XOR]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %0:_(<16 x s8>) = COPY $q0
+ %1:_(<16 x s8>) = COPY $q1
+ %2:_(<16 x s8>) = COPY $q2
+ %3:_(<16 x s8>) = COPY $q3
+ %4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
+ %5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3
+ %6:_(<16 x s1>) = G_XOR %4, %5
+ %7:_(<16 x s8>) = G_ANYEXT %6
+ $q0 = COPY %7:_(<16 x s8>)
+ RET_ReallyLR implicit $q0
+...
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