[llvm] 805da0e - [AMDGPU] Fix some LABEL check lines
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 6 07:53:27 PST 2023
Author: Jay Foad
Date: 2023-02-06T15:53:13Z
New Revision: 805da0e2983a1b97c6299c40cb7fe91b61331c34
URL: https://github.com/llvm/llvm-project/commit/805da0e2983a1b97c6299c40cb7fe91b61331c34
DIFF: https://github.com/llvm/llvm-project/commit/805da0e2983a1b97c6299c40cb7fe91b61331c34.diff
LOG: [AMDGPU] Fix some LABEL check lines
Added:
Modified:
llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
index 52e17bd747c5..d6a97446a705 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
@@ -1,7 +1,7 @@
; RUN: llc -march=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s
-; FUNC-LABEL: {{^}}v_abs_i32:
+; GCN-LABEL: name: s_abs_i32
; GCN: S_ABS_I32
define amdgpu_kernel void @s_abs_i32(ptr addrspace(1) %out, i32 %val) nounwind {
%neg = sub i32 0, %val
@@ -12,7 +12,7 @@ define amdgpu_kernel void @s_abs_i32(ptr addrspace(1) %out, i32 %val) nounwind {
ret void
}
-; FUNC-LABEL: {{^}}v_abs_i32:
+; GCN-LABEL: name: v_abs_i32
; SI: V_SUB_CO_U32_e64
; GFX900: V_SUB_U32_e64
; GCN: V_MAX_I32_e64
@@ -28,7 +28,7 @@ define amdgpu_kernel void @v_abs_i32(ptr addrspace(1) %out, ptr addrspace(1) %sr
ret void
}
-; FUNC-LABEL: {{^}}s_abs_v2i32:
+; GCN-LABEL: name: s_abs_v2i32
; GCN: S_ABS_I32
; GCN: S_ABS_I32
define amdgpu_kernel void @s_abs_v2i32(ptr addrspace(1) %out, <2 x i32> %val) nounwind {
@@ -44,7 +44,7 @@ define amdgpu_kernel void @s_abs_v2i32(ptr addrspace(1) %out, <2 x i32> %val) no
ret void
}
-; FUNC-LABEL: {{^}}v_abs_v2i32:
+; GCN-LABEL: name: v_abs_v2i32
; SI: V_SUB_CO_U32_e64
; GFX900: V_SUB_U32_e64
; GCN: V_MAX_I32_e64
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
index c220620e3bca..153787587987 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-bitreverse.ll
@@ -1,6 +1,6 @@
; RUN: llc -march=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
-; GCN-FUNC: uniform_bitreverse_i32
+; GCN-LABEL: name: uniform_bitreverse_i32
; GCN: S_BREV_B32
define amdgpu_kernel void @uniform_bitreverse_i32(i32 %val, ptr addrspace(1) %out) {
%res = call i32 @llvm.bitreverse.i32(i32 %val)
@@ -8,7 +8,7 @@ define amdgpu_kernel void @uniform_bitreverse_i32(i32 %val, ptr addrspace(1) %ou
ret void
}
-; GCN-FUNC: divergent_bitreverse_i32
+; GCN-LABEL: name: divergent_bitreverse_i32
; GCN: V_BFREV_B32
define amdgpu_kernel void @divergent_bitreverse_i32(i32 %val, ptr addrspace(1) %out) {
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -18,7 +18,7 @@ define amdgpu_kernel void @divergent_bitreverse_i32(i32 %val, ptr addrspace(1) %
ret void
}
-; GCN-FUNC: uniform_bitreverse_i64
+; GCN-LABEL: name: uniform_bitreverse_i64
; GCN: S_BREV_B64
define amdgpu_kernel void @uniform_bitreverse_i64(i64 %val, ptr addrspace(1) %out) {
%res = call i64 @llvm.bitreverse.i64(i64 %val)
@@ -26,7 +26,7 @@ define amdgpu_kernel void @uniform_bitreverse_i64(i64 %val, ptr addrspace(1) %ou
ret void
}
-; GCN-FUNC: divergent_bitreverse_i64
+; GCN-LABEL: name: divergent_bitreverse_i64
; GCN: V_BFREV_B32
; GCN: V_BFREV_B32
define amdgpu_kernel void @divergent_bitreverse_i64(i64 %val, ptr addrspace(1) %out) {
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
index 1eb8e2643134..107948848748 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
@@ -1,7 +1,7 @@
; RUN: llc -march=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX900 %s
-; FUNC-LABEL: {{^}}uniform_add_SIC:
+; GCN-LABEL: name: uniform_add_SIC
; GCN: S_SUB_I32 killed %{{[0-9]+}}, 32
define amdgpu_kernel void @uniform_add_SIC(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
%a = load i32, ptr addrspace(1) %in
@@ -10,7 +10,7 @@ define amdgpu_kernel void @uniform_add_SIC(ptr addrspace(1) %out, ptr addrspace(
ret void
}
-; FUNC-LABEL: {{^}}uniform_add_SIC:
+; GCN-LABEL: name: divergent_add_SIC
; SI: V_SUB_CO_U32_e64 killed %{{[0-9]+}}, 32
; GFX900: V_SUB_U32_e64 killed %{{[0-9]+}}, 32
define amdgpu_kernel void @divergent_add_SIC(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll b/llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
index 5b4e5e66edde..95e096eaa830 100644
--- a/llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
@@ -2,7 +2,7 @@
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; GCN-FUNC: {{^}}vccz_workaround:
+; GCN-LABEL: {{^}}vccz_workaround:
; GCN: s_load_dword [[REG:s[0-9]+]], s[{{[0-9]+:[0-9]+}}],
; GCN: v_cmp_neq_f32_e64 {{[^,]*}}, [[REG]], 0{{$}}
; VCCZ-BUG: s_waitcnt lgkmcnt(0)
@@ -26,7 +26,7 @@ endif:
ret void
}
-; GCN-FUNC: {{^}}vccz_noworkaround:
+; GCN-LABEL: {{^}}vccz_noworkaround:
; GCN: v_cmp_neq_f32_e32 vcc, 0, v{{[0-9]+}}
; GCN-NOT: s_waitcnt lgkmcnt(0)
; GCN-NOT: s_mov_b64 vcc, vcc
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